Method and apparatus for accessing a cache using index prediction

Claim 3

The method of claim 1 further comprising the step of: (h) using prediction for a subsequent access if the portion of the predicted address matches the portion of the physical address in the step (d), and not using prediction on a subsequent access if the portion of the predicted address does not match the portion of the physical address in the step (d).

Claim 4

The method of claim 1 wherein, in a first mode, the virtual address is provided as the predicted address in the step (c), and in a second mode, the buffer of the step (g) provides the predicted address in the step (c).

Claim 5

The method of claim 3 further comprising the step of: (h) using the portion of the physical address stored in the buffer for a subsequent access to the memory array.

Claim 6

A cache memory comprising: an address translator having an input to receive virtual address bits of a current operation, the address translator providing physical address bits at an output; first comparator circuitry having an input from both the physical address bits and the virtual address bits, the first comparator circuitry providing a prediction output indicating whether the physical address bits match the virtual address bits; a first latch coupled to receive the physical address bits from the address translator, the first latch coupled to latch the physical address bits responsive to a predetermined state of the prediction output of the first comparator circuitry, the first latch providing a first latch output; a multiplexer coupled to receive the virtual address bits and the physical address bits, the multiplexer providing cache address bits at a multiplexer output; and second comparator circuitry having an input from both the physical address bits and the cache address bits, the second comparator circuitry providing a verification output indicating whether the physical address bits match the cache address bits.

Claim 7

A cache memory comprising: an address translator having an input to receive virtual address bits of a current operation, the address translator providing physical address bits at an output; first comparator circuitry having an input from both the physical address bits and the virtual address bits, the first comparator circuitry providing a prediction output indicating whether the physical address bits match the virtual address bits; a first latch coupled to receive the physical address bits from the address translator, the first latch coupled to latch the physical address bits responsive to a predetermined state of the prediction output of the first comparator circuitry, the first latch providing a first latch output; a multiplexer coupled to receive the virtual address bits and the physical address bits, the multiplexer providing cache address bits at a multiplexer output; and second comparator circuitry having an input from both the physical address bits and the cache address bits, the second comparator circuitry providing a verification output indicating whether the physical address bits match the cache address bits.

Claim 8

The cache memory of claim 5 further comprising: a second latch coupled to receive the physical address bits from the address translator, the second latch coupled to latch the physical address bits responsive to the predetermined state of the prediction output of the first comparator circuitry, the second latch providing a second latch output, wherein the first latch latches the physical address bits if the current operation is a load operation, and the second latch latches the physical address bits if the current operation is a store operation.

Claim 9

The cache memory of claim 5 wherein the first latch output is coupled to provide an address input to a memory array.

Claim 10

A circuit comprising: a memory array; comparator means, the comparator means having an input from a virtual address, a physical address, and a predicted address, the comparator means providing a first comparator signal indicating whether prediction is to be used on a subsequent data access, and the comparator means providing a second comparator signal indicating whether a current data access is correctly predicted; control logic receiving the first and second comparator signals, the control logic for providing an access address to the memory array responsive to the first and second comparator signals.

Claim 11

A circuit comprising: a memory array; comparator means, the comparator means having an input from a virtual address, a physical address, and a predicted address, the comparator means providing a first comparator signal indicating whether prediction is to be used on a subsequent data access, and the comparator means providing a second comparator signal indicating whether a current data access is correctly predicted; control logic receiving the first and second comparator signals, the control logic for providing an access address to the memory array responsive to the first and second comparator signals.

Claim 12

The circuit of claim 8 wherein the address storage means comprises: a first latch means that latches the predicted cache address when the subsequent access is a load access; and a second latch means that latches the predicted cache address when the subsequent access is a store access.

Claim 13

The circuit of claim 8 wherein the address storage means comprises: a first latch that latches the predicted cache address when the subsequent access is a load access; and a second latch that latches the predicted cache address when the subsequent access is a store access.

Claim 14

The circuit of claim 10 further comprising an instruction decoder, the instruction decoder providing an indication whether the subsequent access is a load access.