US5386527A
Expired / Lapsed
US
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Method and system for high-speed virtual-to-physical address translation and cache tag matching
Assignee: Texas Instruments Inc
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Filing: 1991-12-27
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Granted: 1995-01-31
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Expires: 2011-12-27
Abstract
Abstract A circuit (100) for high-speed virtual-to-physical address translation and cache tag matching comprises a set-associative memory management unit (112) for producing a first predetermined number, N, of candidate physical address signals (132 and 134), and N candidate address hit signals (150 and 152). A set-associative cache (114) produces a second predetermined number M of address tags (168 and 170) and N-by-M array (M00, M01, M10 and M11) of comparison circuits compare the candidate physical addresses (132 and 134) with address tags (168 and 170) gating by the N address hit signals to generate cache hit signals.
Inventors
- 👤 Patrick W. Bosshart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:22
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
112 words
A circuit for high-speed virtual-to-physical address translation and cache tag matching, comprising: circuitry including an N-way set-associative memory for producing a first predetermined plural number, N, of candidate physical addresses and N candidate address hit signals which respectively indicate whether or not said candidate physical addresses are qualified for cache tag matching; an M-way set-associative cache for producing a second predetermined number, M, of address tags; comparison circuitry for comparing each of said N candidate physical addresses with each of said M address tags; and circuitry responsive to said N candidate address hit signals and said comparison circuitry for indicating when a qualified candidate physical address matches one of said address tags.
Claim 2
Dependent Claim
112 words
A circuit for high-speed virtual-to-physical address translation and cache tag matching, comprising: circuitry including an N-way set-associative memory for producing a first predetermined plural number, N, of candidate physical addresses and N candidate address hit signals which respectively indicate whether or not said candidate physical addresses are qualified for cache tag matching; an M-way set-associative cache for producing a second predetermined number, M, of address tags; comparison circuitry for comparing each of said N candidate physical addresses with each of said M address tags; and circuitry responsive to said N candidate address hit signals and said comparison circuitry for indicating when a qualified candidate physical address matches one of said address tags.
Claim 3
Dependent Claim
20 words
The circuit of claim 1, wherein said set-associative memory comprises a two-way set-associative memory for producing two candidate physical addresses.
Claim 4
Dependent Claim
19 words
The circuit of claim 2, wherein said set-associative cache comprises a two-way set-associative cache for producing two address tags.
Claim 5
Dependent Claim
19 words
The circuit of claim 1, wherein said set-associative cache comprises a two-way set-associative cache for producing two address tags.
Claim 6
Dependent Claim
19 words
The circuit of claim 1, wherein said comparison circuitry comprises a plurality of comparison circuits having a wired-OR output.
Claim 7
Dependent Claim
26 words
The circuit of claim 1, wherein said circuitry for producing comprises a plurality of address tag comparators, said address tag comparators further comprising wired OR outputs.
Claim 8
Dependent Claim
16 words
The circuit of claim 1, wherein said comparison circuitry includes an N-by-M array of comparison circuits.
Claim 9
Dependent Claim
22 words
The circuit of claim 7, wherein said cache includes a cache tag random access memory from which said cache tags are produced.
Claim 10
Dependent Claim
18 words
The circuit of claim 8, wherein said comparison circuits are connected to said cache tag random access memory.
Claim 11
Dependent Claim
15 words
The circuit of claim 1, wherein said comparison circuitry includes a dual rail logic input.
Claim 12
Dependent Claim
23 words
The circuit of claim 10, further comprising dual rail logic circuitry to input said candidate physical address signals to said comparison circuit input.
Claim 13
Independent Claim
99 words
A method for high-speed virtual-to-physical address translation and cache tag matching, comprising the steps of: producing a first predetermined plural number, N, of candidate physical addresses; producing a second predetermined number, M, of address tags; comparing each of said N candidate physical addresses with each of said M address tags; generating N candidate address hit signals which respectively indicate whether or not said candidate physical addresses are qualified for cache tag matching; and indicating, in response to said comparing step and said N candidate address hit signals, when a qualified candidate physical address matches one of said address tags.
Claim 14
Independent Claim
99 words
A method for high-speed virtual-to-physical address translation and cache tag matching, comprising the steps of: producing a first predetermined plural number, N, of candidate physical addresses; producing a second predetermined number, M, of address tags; comparing each of said N candidate physical addresses with each of said M address tags; generating N candidate address hit signals which respectively indicate whether or not said candidate physical addresses are qualified for cache tag matching; and indicating, in response to said comparing step and said N candidate address hit signals, when a qualified candidate physical address matches one of said address tags.
Claim 15
Dependent Claim
24 words
The method of claim 12, wherein N=2 and the step of producing two candidate physical addresses includes using a two-way set-associative translation lookaside buffer.
Claim 16
Dependent Claim
20 words
The method of claim 13 wherein M=2 and the step of producing address tags includes using a two-way set-associative cache.
Claim 17
Dependent Claim
21 words
The method of claim 12, wherein m=2 and the step of producing two address tags includes using a two-way set-associative cache.
Claim 18
Dependent Claim
25 words
The method of claim 12, further comprising the step of comparing said candidate physical addresses with said address tags using a dynamic-wired OR comparison circuit.
Claim 19
Dependent Claim
32 words
The method of claim 12, further comprising the step of comparing input virtual addresses to virtual address tags stored within an associative memory management unit, including using a wired OR comparison circuit.
Claim 20
Dependent Claim
20 words
The method of claim 12, wherein said comparing step includes using a comparison circuit having a dual rail logic input.
Claim 21
Dependent Claim
24 words
The method of claim 18, further comprising the step of directing said candidate physical address signals to said comparison circuit using dual rail logic.
References Cited (Backward Citations)
US4899275A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-01-30 | 1998-08-01 | 1999-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-01-30 | 2002-08-01 | 2003-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-01-30 | 2006-08-01 | 2007-01-31 | $7700.00 | Window Closed / Lapsed |