Method for crown type capacitor in dynamic random access memory

Claim 1

A method for manufacturing a crown capacitor for a memory device, comprising the steps of: a) selectively forming isolation areas on the surface of a substrate while leaving device areas of fabrication of semiconductor devices; b) forming device structures within said device areas of said substrate wherein in said device structure includes a capacitor node contact region in said substrate; c) forming a first insulating layer over said device structures and said substrate; d) forming an etch barrier layer over said first insulating layer; e) forming a node contact hole through to said etch barrier layer and said first insulating layer to expose said capacitor node contact region on said substrate; f) forming a plug filling said node contact hole making electrical and mechanical contact with said capacitor node contact region; g) forming a planarizing layer over said etch barrier layer and said plug; h) forming a crown hole in said planarizing layer exposing said plug and surrounding portions of said etch barrier layer; said crown hole is defined by remaining portions of said planarizing layer; i) depositing a first polysilicon layer over said etch barrier layer, said plug, and the remaining planarizing layer partially filling said crown hole; j) forming a sacrificial layer over said first polysilicon layer thereby filling said crown hole; k) removing top portions of said sacrificial layer to expose said first polysilicon layer over said remaining portion of said planarizing layer; said top portions of said sacrificial layer removed by a process selected from the group consisting of etching back and chemical-mechanical polish; l) removing the exposed portions of said first polysilicon layer over the top said remaining portion of said planarizing layer; m) selectively removing the remaining portions of said sacrificial layer and said planarizing layer thereby forming a crown shaped storage electrode; and n) forming a capacitor dielectric layer and a top electrode over said crown shaped storage electrode.

Claim 2

A method for manufacturing a crown capacitor for a memory device, comprising the steps of: a) selectively forming isolation areas on the surface of a substrate while leaving device areas of fabrication of semiconductor devices; b) forming device structures within said device areas of said substrate wherein in said device structure includes a capacitor node contact region in said substrate; c) forming a first insulating layer over said device structures and said substrate; d) forming an etch barrier layer over said first insulating layer; e) forming a node contact hole through to said etch barrier layer and said first insulating layer to expose said capacitor node contact region on said substrate; f) forming a plug filling said node contact hole making electrical and mechanical contact with said capacitor node contact region; g) forming a planarizing layer over said etch barrier layer and said plug; h) forming a crown hole in said planarizing layer exposing said plug and surrounding portions of said etch barrier layer; said crown hole is defined by remaining portions of said planarizing layer; i) depositing a first polysilicon layer over said etch barrier layer, said plug, and the remaining planarizing layer partially filling said crown hole; j) forming a sacrificial layer over said first polysilicon layer thereby filling said crown hole; k) removing top portions of said sacrificial layer to expose said first polysilicon layer over said remaining portion of said planarizing layer; said top portions of said sacrificial layer removed by a process selected from the group consisting of etching back and chemical-mechanical polish; l) removing the exposed portions of said first polysilicon layer over the top said remaining portion of said planarizing layer; m) selectively removing the remaining portions of said sacrificial layer and said planarizing layer thereby forming a crown shaped storage electrode; and n) forming a capacitor dielectric layer and a top electrode over said crown shaped storage electrode.

Claim 13

A method for manufacturing a crown capacitor for a memory device, comprising the steps of: a) selectively forming isolation areas on the surface of a substrate while leaving device areas of fabrication of semiconductor devices; b) forming device structures within said device areas of said substrate wherein in said device structure includes a capacitor node contact region in said substrate; (1) devices comprise gate structures, spacers, a first isolation layer composed of silicon oxide formed by a TetraEthylOrthoSilane (TEOS) process, a second isolation layer composed of silicon oxide, a bit line contact and bit line; c) forming a first insulating layer over said device structures and said substrate; (1) said first insulating layer composed of a material selected from the group consisting of silicon oxide, BPSG, and silicon oxide formed by a Sub atmospheric-oxide process; d) forming an etch barrier layer over said first insulating layer; (1) said etch barrier layer composed of a material selected from the group consisting of silicon nitride, silicon oxynitride and TEOS oxide, and said etch barrier layer having a thickness in a range of between about 50 and 200 Å; e) forming a node contact hole through to said etch barrier layer and said first insulating layer to expose said capacitor node contact region on said substrate; (1) said node contact hole has an open dimension in a range of between about 0.18 and 0.35 μm; f) forming a plug filling said node contact hole making electrical and mechanical contact with said capacitor node contact region; (1) said plug composed of doped polysilicon; said plug formed by depositing a layer of doped polysilicon with a thickness in a range of between about 3000 and 4500 Å and etching back said layer of doped polysilicon; g) forming a planarizing layer over said etch barrier layer and said plug; (1) said planarizing layer composed of a material selected from the group consisting of borophosphosilicate glass, silicon oxide, and spin-on-glass, and a thickness in a range of between about 7000 and 13,000 Å; h) forming a crown hole in said planarizing layer exposing said plug and surrounding portions of said etch barrier layer; said crown hole is defined by remaining portions of said planarizing layer; (1) said crown hole having an open dimension in a range of between about 0.3 and 0.8 μm; i) depositing a first polysilicon layer over said etch barrier layer, said plug, and the remaining planarizing layer partially filling said crown hole; (1) said first polysilicon layer composed of doped polysilicon and having a thickness in a range of between about 300 and 500 Å; j) forming a Hemispherical grains (HSG) layer over said first polysilicon layer; (1) said Hemispherical grains (HSG) layer having a thickness in a range of between about 300 and 700 Å; k) forming a sacrificial layer over said first polysilicon layer thereby filling said crown hole; (1) said sacrificial layer is formed of a material selected from the group consisting of BPSG, silicon oxide, polymer and photo resistant material, and said sacrificial layer having a thickness in a range of between about 4500 and 10,000 Å; l) removing top portions of said sacrificial layer to expose said first polysilicon layer over said remaining portion of said planarizing layer; said top portions of said sacrificial layer removed by a process selected from the group consisting of etching back and chemical-mechanical polish; m) removing the exposed portions of said first polysilicon layer over the top said remaining portion of said planarizing layer; n) selectively removing the remaining portions of said sacrificial layer and said planarizing layer thereby forming a crown shaped storage electrode; and o) forming a capacitor dielectric layer and a top electrode over said crown shaped storage electrode.

Claim 14

A method for manufacturing a crown capacitor for a memory device, comprising the steps of: a) selectively forming isolation areas on the surface of a substrate while leaving device areas of fabrication of semiconductor devices; b) forming device structures within said device areas of said substrate wherein in said device structure includes a capacitor node contact region in said substrate; (1) devices comprise gate structures, spacers, a first isolation layer composed of silicon oxide formed by a TetraEthylOrthoSilane (TEOS) process, a second isolation layer composed of silicon oxide, a bit line contact and bit line; c) forming a first insulating layer over said device structures and said substrate; (1) said first insulating layer composed of a material selected from the group consisting of silicon oxide, BPSG, and silicon oxide formed by a Sub atmospheric-oxide process; d) forming an etch barrier layer over said first insulating layer; (1) said etch barrier layer composed of a material selected from the group consisting of silicon nitride, silicon oxynitride and TEOS oxide, and said etch barrier layer having a thickness in a range of between about 50 and 200 Å; e) forming a node contact hole through to said etch barrier layer and said first insulating layer to expose said capacitor node contact region on said substrate; (1) said node contact hole has an open dimension in a range of between about 0.18 and 0.35 μm; f) forming a plug filling said node contact hole making electrical and mechanical contact with said capacitor node contact region; (1) said plug composed of doped polysilicon; said plug formed by depositing a layer of doped polysilicon with a thickness in a range of between about 3000 and 4500 Å and etching back said layer of doped polysilicon; g) forming a planarizing layer over said etch barrier layer and said plug; (1) said planarizing layer composed of a material selected from the group consisting of borophosphosilicate glass, silicon oxide, and spin-on-glass, and a thickness in a range of between about 7000 and 13,000 Å; h) forming a crown hole in said planarizing layer exposing said plug and surrounding portions of said etch barrier layer; said crown hole is defined by remaining portions of said planarizing layer; (1) said crown hole having an open dimension in a range of between about 0.3 and 0.8 μm; i) depositing a first polysilicon layer over said etch barrier layer, said plug, and the remaining planarizing layer partially filling said crown hole; (1) said first polysilicon layer composed of doped polysilicon and having a thickness in a range of between about 300 and 500 Å; j) forming a Hemispherical grains (HSG) layer over said first polysilicon layer; (1) said Hemispherical grains (HSG) layer having a thickness in a range of between about 300 and 700 Å; k) forming a sacrificial layer over said first polysilicon layer thereby filling said crown hole; (1) said sacrificial layer is formed of a material selected from the group consisting of BPSG, silicon oxide, polymer and photo resistant material, and said sacrificial layer having a thickness in a range of between about 4500 and 10,000 Å; l) removing top portions of said sacrificial layer to expose said first polysilicon layer over said remaining portion of said planarizing layer; said top portions of said sacrificial layer removed by a process selected from the group consisting of etching back and chemical-mechanical polish; m) removing the exposed portions of said first polysilicon layer over the top said remaining portion of said planarizing layer; n) selectively removing the remaining portions of said sacrificial layer and said planarizing layer thereby forming a crown shaped storage electrode; and o) forming a capacitor dielectric layer and a top electrode over said crown shaped storage electrode.