US5955764A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS LSI with projection structure
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1998-08-07
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Granted: 1999-09-21
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Expires: 2018-08-07
Abstract
Abstract A semiconductor device having: a semiconductor substrate of a first conductivity type; a well formed in a surface of said semiconductor substrate, the well being of a second conductivity type opposite to the first conductivity type; a first MOS transistor formed in a surface of a first conductivity type region of the semiconductor substrate; a second MOS transistor formed in a surface of the well; a wiring connected to the gate electrodes of the first and second MOS transistors; and a protection diode with a p-n junction formed in the first conductivity type region and comprising a second conductivity type region electrically connected to the wiring and the first conductivity region of the semiconductor substrate, wherein the wiring and the well are not directly connected electrically. A CMOS type semiconductor integrated circuit device with a long and wide area wiring is realized which can effectively suppress damage to a gate oxide film of a MOSFET.
Inventors
- 👤 Masaki Katsube
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:56
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
172 words
A semiconductor integrated circuit device comprising: a semiconductor chip having an internal region surrounded by a scribe line; a plurality of diffusion regions formed in a surface of said semiconductor chip at the internal region, said diffusion regions being doped with impurity; a plurality of MOS transistors each having a pair of diffusion regions among said plurality of diffusion regions and an insulated gate structure formed on the surface of said semiconductor chip between said pair of diffusion regions; and a plurality of wirings each connected to a gate electrode of one of said plurality of MOS transistors and to another diffusion region among said plurality of diffusion regions, wherein a distance between the gate electrode of each of said plurality of MOS transistors and a nearest scribe line is almost equal to a distance between one diffusion region connected to said wiring connected to the gate electrode or one of said plurality of diffusion regions connected to said wiring, and being nearest to the gate electrode and a nearest scribe line.
Claim 2
Dependent Claim
172 words
A semiconductor integrated circuit device comprising: a semiconductor chip having an internal region surrounded by a scribe line; a plurality of diffusion regions formed in a surface of said semiconductor chip at the internal region, said diffusion regions being doped with impurity; a plurality of MOS transistors each having a pair of diffusion regions among said plurality of diffusion regions and an insulated gate structure formed on the surface of said semiconductor chip between said pair of diffusion regions; and a plurality of wirings each connected to a gate electrode of one of said plurality of MOS transistors and to another diffusion region among said plurality of diffusion regions, wherein a distance between the gate electrode of each of said plurality of MOS transistors and a nearest scribe line is almost equal to a distance between one diffusion region connected to said wiring connected to the gate electrode or one of said plurality of diffusion regions connected to said wiring, and being nearest to the gate electrode and a nearest scribe line.
Claim 3
Dependent Claim
45 words
A semiconductor integrated circuit device according to claim 1, wherein each of parts of said plurality of wirings is connected to a plurality of diffusion regions, and a diffusion region nearest to the gate electrode among said plurality of diffusion regions forms a protection diode.
Claim 4
Dependent Claim
150 words
A semiconductor integrated circuit device comprising: a semiconductor chip having an internal region surrounded by a scribe line; a plurality of diffusion regions formed in a surface of said semiconductor chip at the internal region, said diffusion regions being doped with impurity; a plurality of MOS transistors each having a pair of diffusion regions among said plurality of diffusion regions and an insulated gate structure formed on the surface of said semiconductor chip between said pair of diffusion regions; a plurality of wirings each connected to a gate electrode of one of said plurality of MOS transistors and to another diffusion region among said plurality of diffusion regions; and a quasi scribe line formed in the internal region, said quasi scribe line exposing the surface of said semiconductor substrate or a surface of a conductive layer formed on the surface of said semiconductor surface, at the level of said wiring.
Claim 5
Dependent Claim
150 words
A semiconductor integrated circuit device comprising: a semiconductor chip having an internal region surrounded by a scribe line; a plurality of diffusion regions formed in a surface of said semiconductor chip at the internal region, said diffusion regions being doped with impurity; a plurality of MOS transistors each having a pair of diffusion regions among said plurality of diffusion regions and an insulated gate structure formed on the surface of said semiconductor chip between said pair of diffusion regions; a plurality of wirings each connected to a gate electrode of one of said plurality of MOS transistors and to another diffusion region among said plurality of diffusion regions; and a quasi scribe line formed in the internal region, said quasi scribe line exposing the surface of said semiconductor substrate or a surface of a conductive layer formed on the surface of said semiconductor surface, at the level of said wiring.
Claim 6
Dependent Claim
23 words
A semiconductor integrated circuit device according to claim 3, wherein said quasi scribe line is a diffusion region of an input/output protection circuit.
References Cited (Backward Citations)
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Cited
JPH0434963A
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JPH05190623A
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JPH0661298A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-20 | 2003-03-22 | 2003-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-20 | 2007-03-22 | 2007-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-20 | 2011-03-22 | 2011-09-21 | $7700.00 | Window Closed / Lapsed |