US5955759A
Expired / Lapsed
US
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Reduced parasitic resistance and capacitance field effect transistor
Assignee: International Business Machines Corp
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Filing: 1997-12-11
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Granted: 1999-09-21
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Expires: 2017-12-11
Abstract
Abstract A field effect transistor and method for making the same is described wherein the field effect transistor incorporates a T-shaped gate and source and drain contacts self-aligned with preexisting shallow junction regions. The present invention provides a low resistance gate electrode and self-aligned low resistance source/drain contacts suitable for submicron FET devices, and scalable to smaller device dimensions.
Inventors
- 👤 Khalid EzzEldin Ismail
- 👤 Stephen Anthony Rishton
- 👤 Katherine Lynn Saenger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/017; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10P30/21; H10P30/212; H10P32/00; H10P32/10; H10P32/12; H10P32/17; H10P32/171
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
208 words
A method of forming a field effect transistor comprising the steps of: forming at least one sacrificial layer on at least one surface of a semiconductor substrate, patterning said at least on sacrificial layer to form a sacrificial gate shaped structure surrounded by exposed substrate regions, forming doped semiconductor junction regions in said exposed substrate regions on opposite sides of said sacrificial gate shaped structure, forming source and drain contact metallurgy on said junction regions, said contact metallurgy having a thickness less than the thickness of said gate shaped structure, selectively forming a dielectric cap layer over regions of said source and drain contact metallurgy, wherein said dielectric cap layer has a top surface that is approximately even with the top surface of said sacrificial gate shaped surface, removing said sacrificial gate shaped structure to exposed underlying regions of said substrate and sidewalls of said source and drain contact metallurgy, depositing a gate dielectric to cover said exposed substrate regions and sidewalls and top of said source and drain contact metallurgy, forming a conductive layer on all surfaces of said gate dielectric, said conductive layer also substantially filling the volume formerly occupied by the sacrificial gate shaped structure, and patterning said conductive layer to define a gate electrode.
Claim 2
Independent Claim
208 words
A method of forming a field effect transistor comprising the steps of: forming at least one sacrificial layer on at least one surface of a semiconductor substrate, patterning said at least on sacrificial layer to form a sacrificial gate shaped structure surrounded by exposed substrate regions, forming doped semiconductor junction regions in said exposed substrate regions on opposite sides of said sacrificial gate shaped structure, forming source and drain contact metallurgy on said junction regions, said contact metallurgy having a thickness less than the thickness of said gate shaped structure, selectively forming a dielectric cap layer over regions of said source and drain contact metallurgy, wherein said dielectric cap layer has a top surface that is approximately even with the top surface of said sacrificial gate shaped surface, removing said sacrificial gate shaped structure to exposed underlying regions of said substrate and sidewalls of said source and drain contact metallurgy, depositing a gate dielectric to cover said exposed substrate regions and sidewalls and top of said source and drain contact metallurgy, forming a conductive layer on all surfaces of said gate dielectric, said conductive layer also substantially filling the volume formerly occupied by the sacrificial gate shaped structure, and patterning said conductive layer to define a gate electrode.
Claim 3
Dependent Claim
27 words
The method of claim 1, wherein said semiconductor material is a single crystal material selected from the group consisting of GaAs, InGaAs, InP, Si, InGaAsP and SiGe.
Claim 4
Dependent Claim
71 words
The method of claim 1, wherein said step of forming at least one sacrificial layer includes the step of selecting a bottom layer material from the group consisting of SiO 2 tetraethoxysilane (TEOS) derived oxides, flowable oxides and Si 3 N 4 , and a top layer selected from the group consisting of SiO 2 , tetraethoxysilane (TEOS) derived oxides and flowable oxides, Si 3 N 4 , TiN and silicon.
Claim 5
Dependent Claim
54 words
The method of claim 1, wherein said step of forming source and drain contact metallurgy includes the step of selecting at least one contact metallurgy material from the group consisting of Co, Ni, Pd, Pt, Rh, Ta, Ti, W, conductive silicides of these metals, heavily doped polycrystalline silicon, and heavily doped polycrystalline silicon germanium.
Claim 6
Dependent Claim
40 words
The method of claim 1, wherein said step of forming a dielectric cap on said source and drain contact metallurgy includes the step of selecting a dielectric material from the group consisting of planarizable dielectrics, dielectric oxides and dielectric nitrides.
Claim 7
Dependent Claim
34 words
The method of claim 5, wherein said dielectric cap comprises a planarizable dielectric selected from the group consisting of SiO 2 , tetraethoxysilane (TEOS) derived oxides, flowable oxides and Si 3 N 4 .
Claim 8
Dependent Claim
30 words
The method of claim 5, wherein said dielectric cap comprises a dielectric oxide selected from the group consisting of Tio 2 , Ta 2 O 5 and WO 3 .
Claim 9
Dependent Claim
19 words
The method of claim 1, wherein said step of forming doped semiconductor junctions includes ion implantation and activation annealing.
Claim 10
Dependent Claim
18 words
The method of claim 1, wherein said step of forming doped semiconductor junctions includes gas immersion laser doping.
Claim 11
Dependent Claim
33 words
The method of claim 1, wherein said step of forming doped semiconductor junctions includes the selective epitaxial growth of a dopied semiconductor on said exposed substrate regions not covered by said sacrificial gate.
Claim 12
Dependent Claim
31 words
The method of claim 1, wherein said step of forming source and drain contact metallurgy on said junction regions includes the step of blanket deposition of said contact metallurgy material planarization.
Claim 13
Dependent Claim
15 words
The method of claim 11, wherein said planarization is carried out by chemical mechanical polishing.
Claim 14
Dependent Claim
34 words
The method of claim 11, further comprising the step of recessing top surface of source and drain contact metallurgy to a level below top surface of the sacrificial gate shaped structure by selective etching.
Claim 15
Dependent Claim
34 words
The method of claim 1, wherein said step of forming source and drain contact metallurgy on said junction regions includes the steps of selective growth of said contact metallurgy material on said junction regions.
Claim 16
Dependent Claim
28 words
The method of claim 1, wherein said step of forming said dielectric cap layer includes the step of blanket deposition and planarization of material for said dielectric cap.
Claim 17
Dependent Claim
40 words
The method of claim 1, wherein said step of forming said dielectric cap layer includes the step of growing said cap layer on the contact metallurgy top surface by a process selected from the group consisting of oxidation and nitridation.
Claim 18
Dependent Claim
14 words
The method of claim 16, wherein said oxidation is thermal oxidation or anodic oxidation.
Claim 19
Dependent Claim
41 words
The method of claim 1, further comprising the step of forming dielectric sidewall spacers on the sacrificial gate shaped structure, said dielectric spacers being formed from a material that is substantially different from the material of said sacrificial gate shaped structure.
Claim 20
Dependent Claim
36 words
The method of claim 1, further comprising the step of growing dielectric sidewall spacers on the sidewalls of said source and drain contact metallurgy by a process selected from the group consisting of oxidation and nitridation.
Claim 21
Dependent Claim
15 words
The method of claim 19, wherein said oxidation is a thermal oxidation or anodic oxidation.
Claim 22
Independent Claim
168 words
A method of forming a field effect transistor comprising the steps of: forming at least one sacrificial layer on at least one surface of a semiconductor substrate, patterning said at least on sacrificial layer to form a sacrificial gate shaped structure surrounded by exposed substrate regions, forming doped semiconductor junction regions in said exposed substrate regions on opposite sides of said sacrificial gate shaped structure, selectively forming source and drain contact metallurgy on said junction regions, selectively forming a dielectric cap on said source and drain contact metallurgy, removing said sacrificial gate shaped structure to exposed underlying regions of said substrate and sidewalls of said source and drain contact metallurgy, depositing a gate dielectric to cover said exposed substrate regions and sidewalls and top of said source and drain contact metallurgy, forming a conductive layer on all surfaces of said gate dielectric, said conductive layer also substantially filling the volume formerly occupied by the sacrificial gate shaped structure, and patterning said conductive layer to define a gate electrode.
Claim 23
Independent Claim
168 words
A method of forming a field effect transistor comprising the steps of: forming at least one sacrificial layer on at least one surface of a semiconductor substrate, patterning said at least on sacrificial layer to form a sacrificial gate shaped structure surrounded by exposed substrate regions, forming doped semiconductor junction regions in said exposed substrate regions on opposite sides of said sacrificial gate shaped structure, selectively forming source and drain contact metallurgy on said junction regions, selectively forming a dielectric cap on said source and drain contact metallurgy, removing said sacrificial gate shaped structure to exposed underlying regions of said substrate and sidewalls of said source and drain contact metallurgy, depositing a gate dielectric to cover said exposed substrate regions and sidewalls and top of said source and drain contact metallurgy, forming a conductive layer on all surfaces of said gate dielectric, said conductive layer also substantially filling the volume formerly occupied by the sacrificial gate shaped structure, and patterning said conductive layer to define a gate electrode.
Claim 24
Dependent Claim
106 words
A field effect transistor comprising: a semiconductor substrate, two spaced apart doped semiconductor regions forming source and drain junction regions and defining a channel substrate region therebetween, a first conductive layer over said junction regions, said first conductor layer forming source and drain contact metallurgy, a first dielectric layer on top surfaces of said contact metallurgy, a gate dielectric on said channel substrate region extending over sidewalls and top surfaces of said contact metallurgy, and a gate having a T-shaped cross section comprising a second conductive layer on said gate dielectric and extending over first dielectric layer and portion of the source and drain contact metallurgy.
Claim 25
Dependent Claim
106 words
A field effect transistor comprising: a semiconductor substrate, two spaced apart doped semiconductor regions forming source and drain junction regions and defining a channel substrate region therebetween, a first conductive layer over said junction regions, said first conductor layer forming source and drain contact metallurgy, a first dielectric layer on top surfaces of said contact metallurgy, a gate dielectric on said channel substrate region extending over sidewalls and top surfaces of said contact metallurgy, and a gate having a T-shaped cross section comprising a second conductive layer on said gate dielectric and extending over first dielectric layer and portion of the source and drain contact metallurgy.
Claim 26
Dependent Claim
29 words
A field effect transistor comprising the structure of claim 22, said structure further comprising dielectric sidewall spacers interposed between the gate dielectric and the sidewalls of the contact metallurgy.
Claim 27
Dependent Claim
21 words
A field effect transistor comprising the structure of claim 22, said structure having no gate dielectric on sidewalls or source/drain top.
Claim 28
Dependent Claim
21 words
A field effect transistor comprising the structure of claim 23, said structure having no gate dielectric on sidewalls or source/drain top.
Claim 29
Independent Claim
224 words
A method of forming a field effect transistor comprising the steps of: forming at least one sacrificial layer on a single crystal semiconductor substrate, patterning said at least on sacrificial layer to form a sacrificial gate shaped structure surrounded by exposed substrate regions, forming doped semiconductor junction regions in said exposed substrate regions on opposite sides of said sacrificial gate shaped structure, forming source and drain contact metallurgy on said junction regions, said contact metallurgy having a thickness less than the thickness of said gate shaped structure, selectively forming a dielectric cap layer over regions of said source and drain contact metallurgy, wherein of said dielectric cap layer has a top surface that is approximately even with top surface of said sacrificial gate shaped surface, removing said sacrificial gate shaped structure to exposed underlying regions of said substrate and sidewalls of said source and drain contact metallurgy, depositing a gate dielectric to cover said exposed substrate regions but not said sidewalls of said source and drain contact metallurgy, forming dielectric sidewall spacers on said side walls of said source and drain contact metallurgy, forming a conductive layer over said gate dielectric and said source and drain contact metallurgy, said conductive layer also substantially filling the volume formerly occupied by the sacrificial gate shaped structure, and patterning said conductive layer to define a gate electrode.
Claim 30
Independent Claim
224 words
A method of forming a field effect transistor comprising the steps of: forming at least one sacrificial layer on a single crystal semiconductor substrate, patterning said at least on sacrificial layer to form a sacrificial gate shaped structure surrounded by exposed substrate regions, forming doped semiconductor junction regions in said exposed substrate regions on opposite sides of said sacrificial gate shaped structure, forming source and drain contact metallurgy on said junction regions, said contact metallurgy having a thickness less than the thickness of said gate shaped structure, selectively forming a dielectric cap layer over regions of said source and drain contact metallurgy, wherein of said dielectric cap layer has a top surface that is approximately even with top surface of said sacrificial gate shaped surface, removing said sacrificial gate shaped structure to exposed underlying regions of said substrate and sidewalls of said source and drain contact metallurgy, depositing a gate dielectric to cover said exposed substrate regions but not said sidewalls of said source and drain contact metallurgy, forming dielectric sidewall spacers on said side walls of said source and drain contact metallurgy, forming a conductive layer over said gate dielectric and said source and drain contact metallurgy, said conductive layer also substantially filling the volume formerly occupied by the sacrificial gate shaped structure, and patterning said conductive layer to define a gate electrode.
Claim 31
Dependent Claim
43 words
The method of claim 26, wherein said step of forming said dielectric sidewall spacers on said sidewalls of said source and drain contact metallurgy further includes selecting a spacer dielectric that is substantially different from the material of said sacrificial gate shaped structure.
Claim 32
Dependent Claim
37 words
The method of claim 26, wherein the step of forming said dielectric sidewall spacers on the sidewalls of said source and drain contact metallurgy is by a process selected from the group consisting of oxidation and nitridation.
Claim 33
Dependent Claim
14 words
The method of claim 28, wherein said oxidation is thermal oxidation or anodic oxidation.
References Cited (Backward Citations)
US5089863A
Cited
US5272100A
Cited
US5231038A
Cited
US5405787A
Cited
JPH04180633A
Cited
US5196357A
Cited
US5268330A
Cited
JPH06350085A
Cited
TW266313B
Cited
US5464782A
Cited
TW250579B
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-09-20 | 2003-03-22 | 2003-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-20 | 2007-03-22 | 2007-09-21 | $3760.00 | Window Closed / Lapsed |
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