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US5953619A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device with perovskite capacitor and its manufacture method

Assignee: Fujitsu Semiconductor Ltd
•
Filing: 1998-03-18
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Granted: 1999-09-14
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Expires: 2018-03-18
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Abstract

Abstract A method of manufacturing a semiconductor device which has the steps of: forming an insulated gate field effect transistor of a first conductivity type on a semiconductor substrate,; forming a first insulating film over the semiconductor substrate, the first insulating film covering the insulated gate electrode; forming a contact window through the first insulating film to at least one of the source/drain regions; embedding a metal plug in the contact window; forming a second insulating film having an oxygen blocking function on the first insulating film, the second insulating film covering the metal plug; forming a capacitor lower electrode on the second insulating film; forming a dielectric oxide film having a perovskite crystal structure on the lower electrode; annealing the semiconductor substrate in an oxygen-containing atmosphere; and forming a capacitor upper electrode on the dielectric oxide film. A semiconductor device can be realized which has capacitors with dielectric oxide films of a perovskite crystal structure having a high dielectric constant.

Inventors

  • 👤 Hisashi Miyazawa
  • 👤 Kenichi Inoue
  • 👤 Tatsuya Yamazaki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 02:19
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/50; H10D; H10D1/00; H10D1/60; H10D1/68; H10D1/682; H10B12/01; H10B12/09; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0181; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/853

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 159 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulated gate field effect transistor on a semiconductor substrate, the insulated gate field effect transistor having an insulated gate electrode and source/drain regions of a first conductivity type; forming a first insulating film over the semiconductor substrate, the first insulating film covering the insulated gate electrode; forming a contact window through the first insulating film to at least one of the source/drain regions; embedding a metal plug in the contact window; forming a second insulating film having an oxygen blocking function on the first insulating film, the second insulating film covering the metal plug; forming a capacitor lower electrode on the second insulating film; forming a dielectric oxide film having a perovskite crystal structure on the lower electrode; annealing the semiconductor substrate in an oxygen-containing atmosphere after said step of forming the dielectric oxide film; and forming a capacitor upper electrode on the dielectric oxide film.
Claim 2
Independent Claim 159 words
A method of manufacturing a semiconductor device comprising the steps of: forming an insulated gate field effect transistor on a semiconductor substrate, the insulated gate field effect transistor having an insulated gate electrode and source/drain regions of a first conductivity type; forming a first insulating film over the semiconductor substrate, the first insulating film covering the insulated gate electrode; forming a contact window through the first insulating film to at least one of the source/drain regions; embedding a metal plug in the contact window; forming a second insulating film having an oxygen blocking function on the first insulating film, the second insulating film covering the metal plug; forming a capacitor lower electrode on the second insulating film; forming a dielectric oxide film having a perovskite crystal structure on the lower electrode; annealing the semiconductor substrate in an oxygen-containing atmosphere after said step of forming the dielectric oxide film; and forming a capacitor upper electrode on the dielectric oxide film.
Claim 3
Dependent Claim 25 words
A method of manufacturing a semiconductor device according to claim 1, wherein said annealing step is performed at a temperature of 700° C. or higher.
Claim 4
Dependent Claim 70 words
A method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: forming a third insulating film over the semiconductor substrate, the third insulating film covering the capacitor upper electrode; forming contact holes through the third insulating film to the metal plug and to the capacitor upper or lower electrode; and connecting a local interconnect between the metal plug and the capacitor upper or lower electrode.
Claim 5
Dependent Claim 40 words
A method of manufacturing a semiconductor device according to claim 1, wherein said step of forming the second insulating film includes a sub-step of forming a nitride film and a sub-step of forming an oxide film on the nitride film.
Claim 6
Dependent Claim 40 words
A method of manufacturing a semiconductor device according to claim 1, wherein said step of forming the capacitor lower electrode includes a sub-step of forming a Ti film and a sub-step of forming a Pt film on the Ti film.
Claim 7
Dependent Claim 44 words
A method of manufacturing a semiconductor device according to claim 5, wherein said sub-step of forming the Ti film sets a thickness of the Ti film so that the (1 1 1) orientation of the dielectric oxide film is realized at said annealing step.
Claim 8
Dependent Claim 33 words
A method of manufacturing a semiconductor device according to claim 1, wherein said step of forming the dielectric oxide film forms a dielectric film containing at least one of PZT, SBT, and BST.
Claim 9
Dependent Claim 48 words
A method of manufacturing a semiconductor device according to claim 1, wherein said step of forming the dielectric oxide film forms a PZT film whose Pb composition is set to such a value that the dielectric oxide film realizes the (1 1 1) orientation after said annealing step.

References Cited (Backward Citations)

JPH0513708A Cited
US5442585A Cited
US5739563A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-09-13 2003-03-15 2003-09-14 $2000.00 Window Closed / Lapsed
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11.5 Years (Year 12) 2010-09-13 2011-03-15 2011-09-14 $7700.00 Window Closed / Lapsed

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