Patent US5953265A successfully refreshed from Google Patents.
US5953265A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory having error detection and correction
Assignee: EMC Corp
•
Filing: 1997-09-29
•
Granted: 1999-09-14
•
Expires: 2017-09-29
Abstract
Abstract A memory system having: a plurality of memory packages for storing words, each one of the packages being adapted to store a plurality of different bits of the word; and an error detection and correction system adapted to detect an error produced in any one of the packages in storing the digital word. With such an arrangement, an error produced by a defect in one of plurality of memory packages, each adapted to store more than one bit of a digital word, may be corrected without requiring changes to other EDACs used in a system employing such memory system. The memory system has a buffer for storing a digital word having N bits of data and M redundant bits for error detection and correction. An error correction code generator is provided for converting the digital word into a second digital word having N bits of data and P redundant bits for error detection and correction. A memory is used for storing the N+P digital word. A error correction code detector corrects an error the data read from the memory.
Inventors
- 👤 John K. Walton
- 👤 Christopher S. Maclellan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:39
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/1028
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
100 words
A memory system, comprising: a buffer for storing a digital word having N bits of data and M redundant bits for error detection and correction; a error correction code generator for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section adapted to store the second digital word and to have read therefrom such stored second digital word; and an error correction code unit for correcting an error in the second digital word read from the memory.
Claim 2
Dependent Claim
100 words
A memory system, comprising: a buffer for storing a digital word having N bits of data and M redundant bits for error detection and correction; a error correction code generator for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section adapted to store the second digital word and to have read therefrom such stored second digital word; and an error correction code unit for correcting an error in the second digital word read from the memory.
Claim 3
Independent Claim
100 words
A method for operating a memory system, comprising: receiving a digital word having N bits of data and M redundant bits for error detection and correction; converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; storing in a memory section the second digital word; reading the stored second digital word from the memory section; and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 4
Independent Claim
100 words
A method for operating a memory system, comprising: receiving a digital word having N bits of data and M redundant bits for error detection and correction; converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; storing in a memory section the second digital word; reading the stored second digital word from the memory section; and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 5
Independent Claim
119 words
A method for operating a memory system, comprising: receiving a first digital word having N bits of data and M redundant bits for error detection and correction; converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; storing in a memory section the second digital word; correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section; and determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 6
Independent Claim
119 words
A method for operating a memory system, comprising: receiving a first digital word having N bits of data and M redundant bits for error detection and correction; converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; storing in a memory section the second digital word; correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section; and determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 7
Independent Claim
158 words
A method for operating a memory system, comprising: receiving a digital word having N bits of data and M redundant bits for error detection and correction; converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word reading the stored second digital word from the memory section; and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 8
Independent Claim
158 words
A method for operating a memory system, comprising: receiving a digital word having N bits of data and M redundant bits for error detection and correction; converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word reading the stored second digital word from the memory section; and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 9
Independent Claim
173 words
A method for operating a memory system, comprising: receiving a first digital word having N bits of data and M redundant bits for error detection and correction; converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word; reading the stored second digital word from the memory section; correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section; and determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 10
Independent Claim
173 words
A method for operating a memory system, comprising: receiving a first digital word having N bits of data and M redundant bits for error detection and correction; converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word; reading the stored second digital word from the memory section; correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section; and determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 11
Independent Claim
193 words
A method for operating a memory system, comprising: receiving a digital word having N bits of data and M redundant bits for error detection and correction; converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word; reading the stored second digital word from the memory section; and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 12
Independent Claim
193 words
A method for operating a memory system, comprising: receiving a digital word having N bits of data and M redundant bits for error detection and correction; converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word; reading the stored second digital word from the memory section; and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 13
Independent Claim
215 words
A method for operating a memory system, comprising: receiving a first digital word having N bits of data and M redundant bits for error detection and correction; converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word;; reading the stored second digital word from the memory section; correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section; and determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 14
Independent Claim
215 words
A method for operating a memory system, comprising: receiving a first digital word having N bits of data and M redundant bits for error detection and correction; converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word; storing in a memory section the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word;; reading the stored second digital word from the memory section; correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section; and determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 15
Dependent Claim
115 words
A memory system, comprising: an error correction code generator for receiving a digital word having N bits of data and M redundant bits for error detection and correction and for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section for storing the second digital word; an error detection and correction unit for receiving the stored second digital word read from the memory section, and for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 16
Dependent Claim
115 words
A memory system, comprising: an error correction code generator for receiving a digital word having N bits of data and M redundant bits for error detection and correction and for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section for storing the second digital word; an error detection and correction unit for receiving the stored second digital word read from the memory section, and for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 17
Dependent Claim
137 words
A memory system, comprising: a error correction code generator for receiving a first digital word having N bits of data and M redundant bits for error detection and correction and for converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section for storing the second digital word from the memory section; an error detection and correction unit for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section and for determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 18
Dependent Claim
137 words
A memory system, comprising: a error correction code generator for receiving a first digital word having N bits of data and M redundant bits for error detection and correction and for converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section for storing the second digital word from the memory section; an error detection and correction unit for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section and for determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 19
Dependent Claim
160 words
A memory system, comprising: an error correction code generator for receiving a digital word having N bits of data and M redundant bits for error detection and correction and for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; a memory section for storing the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word; a error detection and correction unit for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 20
Dependent Claim
160 words
A memory system, comprising: an error correction code generator for receiving a digital word having N bits of data and M redundant bits for error detection and correction and for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; a memory section for storing the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word; a error detection and correction unit for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 21
Dependent Claim
188 words
A memory system, comprising: an error correction code generator for receiving a first digital word having N bits of data and M redundant bits for error detection and correction and for converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section for storing the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word; a error detection and correction unit for reading the stored second digital word from the memory section, for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section, and for determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 22
Dependent Claim
188 words
A memory system, comprising: an error correction code generator for receiving a first digital word having N bits of data and M redundant bits for error detection and correction and for converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is different from M; a memory section for storing the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word; a error detection and correction unit for reading the stored second digital word from the memory section, for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section, and for determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 23
Dependent Claim
207 words
A memory system, comprising: an error correction code generator for receiving a digital word having N bits of data and M redundant bits for error detection and correction and for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; a memory section for storing the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word; an error detection and correction unit for reading the stored second digital word from the memory section and for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 24
Dependent Claim
207 words
A memory system, comprising: an error correction code generator for receiving a digital word having N bits of data and M redundant bits for error detection and correction and for converting the digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word and where P is different from M; a memory section for storing the second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word; an error detection and correction unit for reading the stored second digital word from the memory section and for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section.
Claim 25
Dependent Claim
219 words
A memory system, comprising: an error correction code generator for receiving a first digital word having N bits of data and M redundant bits for error detection and correction and for converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word; a memory section for storing such second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word;; an error detection and correction unit for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section and for determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
Claim 26
Dependent Claim
219 words
A memory system, comprising: an error correction code generator for receiving a first digital word having N bits of data and M redundant bits for error detection and correction and for converting the first digital word into a second digital word having the N bits of data and P redundant bits for error detection and correction, where P is derived from the N bits of the received digital word; a memory section for storing such second digital word, such memory section comprising a plurality of memory packages, an error in storing or retrieving N bits of the data of the second digital word in any one of the packages being correctable by the P redundant bits of such stored second digital word and an error in storing or retrieving N bits of the data of the second digital word in two of the packages being detectable by the P redundant bits of such stored second digital word;; an error detection and correction unit for detecting and correcting an error in the second digital word read from the memory in response to the P redundant bits read from the memory section and for determining, in response to the M bits of the first digital word, whether there is an error in the data portion of the received first digital word.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |