US5952857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit achieving reliable data latching
Assignee: Socionext Inc
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Filing: 1998-04-21
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Granted: 1999-09-14
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Expires: 2018-04-21
Abstract
Abstract A semiconductor integrated circuit receiving a plurality of input signals each exhibiting a signal-level change during a predetermined time span includes a timing-detection circuit which detects timing of said signal-level change of said input signals, and detects which input signal is furthest behind in terms of a signal-level-change timing among said plurality of input signals within said predetermined time span. The semiconductor integrated circuit further includes first delay-adjustment circuits which delay said plurality of input signals, respectively, in response to an output signal from the timing-detection circuit to generate delayed input signals such that signal-level-change timings of said delayed input signals are aligned to said signal-level-change timing of said furthest behind input signal, and latch circuits each latching a respective one of said delayed input signals at the same timing.
Inventors
- 👤 Takaaki Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:58
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H03K; H03K17/00; H03K17/002; H03K5/00; H03K5/13; H03K5/135; H03L7/07; H04; H04L; H04L7/00; H04L7/0008; H04L7/0012; H04L7/0016; H04L7/0033; H04L7/0037; H04L7/02; H04L7/0041
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
126 words
A semiconductor integrated circuit receiving a plurality of input signals each exhibiting a signal-level change during a predetermined time span, said semiconductor integrated circuit comprising: a timing-detection circuit which detects timing of said signal-level change of said input signals, and outputs which input signal is furthest behind in terms of a signal-level-change timing among said plurality of input signals within said predetermined time span; first delay-adjustment circuits which receive and delay said plurality of input signals, respectively, in response to an output signal from the timing-detection circuit to generate delayed input signals such that signal-level-change timings of said delayed input signals are aligned to said signal-level-change timing of said furthest behind input signal; and latch circuits each latching a respective one of said delayed input signals.
Claim 2
Dependent Claim
126 words
A semiconductor integrated circuit receiving a plurality of input signals each exhibiting a signal-level change during a predetermined time span, said semiconductor integrated circuit comprising: a timing-detection circuit which detects timing of said signal-level change of said input signals, and outputs which input signal is furthest behind in terms of a signal-level-change timing among said plurality of input signals within said predetermined time span; first delay-adjustment circuits which receive and delay said plurality of input signals, respectively, in response to an output signal from the timing-detection circuit to generate delayed input signals such that signal-level-change timings of said delayed input signals are aligned to said signal-level-change timing of said furthest behind input signal; and latch circuits each latching a respective one of said delayed input signals.
Claim 3
Dependent Claim
91 words
The semiconductor integrated circuit as claimed in claim 1, further comprising: a second delay-adjustment circuit which receives a clock signal, and delays said clock signal to align a signal-level-change timing of said clock signal to said signal-level-change timing of said furthest behind input signal; and a clock-delay circuit which further introduces a predetermined delay to said clock signal delayed by said second delay-adjustment circuit so as to generate a delayed clock signal, wherein said latch circuits use said delayed clock signal as a synchronization signal to latch said delayed input signals.
Claim 4
Dependent Claim
117 words
The semiconductor integrated circuit as claimed in claim 2, wherein each of said first delay-adjustment circuits comprises: a signal-delay circuit which receives a respective input signal of said plurality of input signals, and delays said respective input signal by an adjusted delay amount; a phase-comparison circuit which compares a signal-level-change timing of said respective input signal delayed by said signal-delay circuit with said signal-level-change timing of said furthest behind input signal; and a delay-control circuit which adjusts said adjusted delay amount based on comparison results of said phase-comparison circuit such that said signal-level-change timing of said respective input signal delayed by said signal-delay circuit is substantially equal to said signal-level-change timing of said furthest behind input signal.
Claim 5
Dependent Claim
69 words
The semiconductor integrated circuit as claimed in claim 2, wherein said timing-detection circuit comprises: a plurality of latches each provided for a corresponding one of said plurality of input signals, each of said plurality of latches being set when a corresponding one of said plurality of input signals exhibits a signal-level change; and a circuit which changes an output thereof when all of said plurality of latches are set.
Claim 6
Dependent Claim
23 words
The semiconductor integrated circuit as claimed in claim 2, wherein said predetermined time span is equal to one cycle of said clock signal.
Claim 7
Dependent Claim
24 words
The semiconductor integrated circuit as claimed in claim 2, wherein said first delay-adjustment circuits and said second delay-adjustment circuit operate during a calibration mode.
Claim 8
Dependent Claim
25 words
The semiconductor integrated circuit as claimed in claim 6, further comprising a command-detection circuit which sets said calibration mode in response to a command input.
Claim 9
Dependent Claim
27 words
The semiconductor integrated circuit as claimed in claim 6, further comprising a power-on-detection circuit which sets said calibration mode upon detecting power-on of said semiconductor integrated circuit.
Claim 10
Dependent Claim
42 words
The semiconductor integrated circuit as claimed in claim 6, further comprising a detection-and-setting circuit which monitors a power voltage and temperature, and sets said calibration mode in response to a change in at least one of said power voltage and said temperature.
Claim 11
Dependent Claim
90 words
The semiconductor integrated circuit as claimed in claim 9, said detection-and-setting circuit comprises: a detection circuit which monitors said power voltage and said temperature, and detects a change in at least one of said power voltage and said temperature; and setting circuit which sets said calibration mode when said detection circuit detects said change, and counts a number as to how many times said timing-detection circuit detects said signal-level-change timing of said furthest behind input signal, said setting circuit ending said calibration mode when said number becomes a predetermined number.
Claim 12
Dependent Claim
64 words
A semiconductor integrated circuit comprising: a timing-detection circuit detecting and outputting an input signal which is furthest behind in terms of timings among a plurality of input signals; a first delay-adjustment circuit which delays said plurality of input signals to generate delayed input signals such that said delayed input signals are aligned to said input signal; and latch circuits latching said delayed input signals.
Claim 13
Dependent Claim
64 words
A semiconductor integrated circuit comprising: a timing-detection circuit detecting and outputting an input signal which is furthest behind in terms of timings among a plurality of input signals; a first delay-adjustment circuit which delays said plurality of input signals to generate delayed input signals such that said delayed input signals are aligned to said input signal; and latch circuits latching said delayed input signals.
Claim 14
Dependent Claim
81 words
The semiconductor integrated circuit as claimed in claim 11, further comprising: a second delay-adjustment circuit which receives a clock signal, and delays said clock signal to align said clock signal to said input signal; and a clock-delay circuit which further introduces a predetermined delay to said clock signal delayed by said second delay-adjustment circuit so as to generate a delayed clock signal, wherein said latch circuits use said delayed clock signal as a synchronization signal to latch said delayed input signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-13 | 2003-03-15 | 2003-09-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-13 | 2007-03-15 | 2007-09-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-13 | 2011-03-15 | 2011-09-14 | $7700.00 | Window Closed / Lapsed |