Apparatus and method for shutdown of wireless communications mobile station with multiple clocks

Claim 2

A wireless communications mobile station comprising: a. radio frequency circuitry for receiving and modulating radio signals; b. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals; c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals, wherein said baseband processing circuitry comprises a control processor and a digital signal processor and wherein the control processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock; d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals; e. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry; f. a first reference clock operationally connected to said baseband processing circuitry which provides an approximate 13 MHz reference signal; g. a second clock which runs at a frequency lower than 13 Mhz; and h. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry.

Claim 3

A wireless communications mobile station comprising: a. radio frequency circuitry for receiving and modulating radio signals; b. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals; c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals, wherein said baseband processing circuitry comprises a control processor and a digital signal processor and wherein the digital signal processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock; d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals; e. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry; f. a first reference clock operationally connected to said baseband processing circuitry which provides an approximate 13 MHz reference signal; g. a second clock which runs at a frequency lower than 13 Mhz; and h. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry.

Claim 4

A wireless communications mobile station comprising: a. radio frequency circuitry for receiving and modulating radio signals; b. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals; c. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals, wherein said baseband processing circuitry comprises a control processor and a digital signal processor and wherein the digital signal processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock; d. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals; e. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry; f. a first reference clock operationally connected to said baseband processing circuitry which provides an approximate 13 MHz reference signal; g. a second clock which runs at a frequency lower than 13 Mhz; and h. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry.

Claim 5

Digital circuitry for a wireless communications mobile station comprising: a. baseband processing circuitry for processing digitized radio signals, said baseband processing circuitry comprises a control processor and a digital signal processor wherein the control processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock; b. a first reference clock operationally connected to said baseband processing circuitry and providing an approximate 13 MHz reference signal, c. a second clock which runs at a frequency lower than 13 MHz; and d. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a mode in which said first clock is shut down and the second clock serves as a timing reference for the sleep logic circuitry.

Claim 6

Digital circuitry for a wireless communications mobile station comprising: a. baseband processing circuitry for processing digitized radio signals, said baseband processing circuitry comprises a control processor and a digital signal processor wherein the control processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock; b. a first reference clock operationally connected to said baseband processing circuitry and providing an approximate 13 MHz reference signal, c. a second clock which runs at a frequency lower than 13 MHz; and d. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a mode in which said first clock is shut down and the second clock serves as a timing reference for the sleep logic circuitry.

Claim 7

Digital circuitry for a wireless communications mobile station comprising: a. baseband processing circuitry for processing digitized radio signals, said baseband processing circuitry comprises a control processor and a digital signal processor wherein the digital signal processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock; b. a first reference clock operationally connected to said baseband processing circuitry and providing an approximate 13 MHz reference signal; c. a second clock which runs at a frequency lower than 13 MHz; and d. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a mode in which said first clock is shut down and the second clock serves as a timing reference for the sleep logic circuitry.

Claim 8

Digital circuitry for a wireless communications mobile station comprising: a. baseband processing circuitry for processing digitized radio signals, said baseband processing circuitry comprises a control processor and a digital signal processor wherein the digital signal processor is operationally connected to the first clock via a phase lock loop which up-converts the frequency of the reference signal from the first clock; b. a first reference clock operationally connected to said baseband processing circuitry and providing an approximate 13 MHz reference signal; c. a second clock which runs at a frequency lower than 13 MHz; and d. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a mode in which said first clock is shut down and the second clock serves as a timing reference for the sleep logic circuitry.

Claim 9

A wireless communications system comprising: a. a mobile station, b. a base station subsystem which controls the radio link with the mobile station, and c. a network subsystem which is interfaced with a public fixed network and the base station subsystem, wherein said mobile station comprises the following: i. radio frequency circuitry for receiving and modulating radio signals; ii. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals; iii. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals; iv. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals, v. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry; vi. a first reference clock operationally connected to said baseband processing circuitry providing a first reference signal; vii. a second clock which runs at a freguency lower than the frequency of the first clock wherein said second clock runs between 32 kHz minus 50 ppm and 32 kHz plus 50 ppm; and viii. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry, ix. a calibrator to calibrate the signal of the second clock prior to sleep mode.

Claim 10

A wireless communications system comprising: a. a mobile station, b. a base station subsystem which controls the radio link with the mobile station, and c. a network subsystem which is interfaced with a public fixed network and the base station subsystem, wherein said mobile station comprises the following: i. radio frequency circuitry for receiving and modulating radio signals; ii. first mixed signal circuitry operationally connected to the radio frequency circuitry for converting the modulated radio signals to digitized signals; iii. baseband processing circuitry operationally connected to said first mixed signal circuitry for processing said digitized signals; iv. second mixed signal circuitry operationally connected to the baseband processing circuitry for converting processed digitized signals to analog signals, v. a speaker operationally connected to said second mixed signal circuitry for communicating speech derived from analog signals input into the speaker from said second mixed signal circuitry; vi. a first reference clock operationally connected to said baseband processing circuitry providing a first reference signal; vii. a second clock which runs at a freguency lower than the frequency of the first clock wherein said second clock runs between 32 kHz minus 50 ppm and 32 kHz plus 50 ppm; and viii. sleep logic circuitry operationally connected to said first clock and said second clock, such that said sleep logic circuitry causes the mobile station to enter a sleep mode in which said first clock is turned off and the second clock serves as a timing reference for the sleep logic circuitry, ix. a calibrator to calibrate the signal of the second clock prior to sleep mode.