Patent US5949439A successfully refreshed from Google Patents.
US5949439A
Expired / Lapsed
US
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Computing apparatus and operating method using software queues to improve graphics performance
Assignee: ATI Technologies ULC
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Filing: 1996-08-15
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Granted: 1999-09-07
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Expires: 2016-08-15
Abstract
Abstract A software queue located in an offscreen portion of video memory is used as a large-capacity software queue for queuing messages to a graphics accelerator. Although the software queue is typically stored in a dynamic RAM (DRAM) memory, advantages of faster static RAM (SRAM) are achieved by shadowing some of the queuing information in SRAM. Usage of a large-capacity software queue in video DRAM memory and information shadowing in faster SRAM memory achieves an advantageous balance between throughput speed and queue size. The large-capacity of the software queue ensures that the queue is virtually never filled to capacity so that delays while awaiting free space in the queue are virtually never incurred. The capacity of the software queue is determined in software and is therefore adaptable to match a particular graphics application.
Inventors
- 👤 Roey Ben-Yoseph
- 👤 Paul Hsieh
- 👤 Wade K. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:13
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/54; G06F9/546; G06T; G06T1/00; G06T1/20
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
118 words
A computing apparatus comprising: a processor; an accelerator coupled to the processor; a central storage coupled to the processor without intermediate hardware FIFO buffering and controlled by the processor, the central storage also being coupled to the accelerator without intermediate hardware FIFO buffering; and a software routine including a processor routine executing on the processor and an accelerator dispatcher routine executing on the accelerator, the software routine further including: a configuration routine allocating a queue within the central storage; a message posting routine executing on the processor and writing a message to the queue; and a message consuming routine executing on the accelerator, reading a message from the queue, and activating the message for performance by the accelerator.
Claim 2
Dependent Claim
118 words
A computing apparatus comprising: a processor; an accelerator coupled to the processor; a central storage coupled to the processor without intermediate hardware FIFO buffering and controlled by the processor, the central storage also being coupled to the accelerator without intermediate hardware FIFO buffering; and a software routine including a processor routine executing on the processor and an accelerator dispatcher routine executing on the accelerator, the software routine further including: a configuration routine allocating a queue within the central storage; a message posting routine executing on the processor and writing a message to the queue; and a message consuming routine executing on the accelerator, reading a message from the queue, and activating the message for performance by the accelerator.
Claim 3
Dependent Claim
14 words
A computing apparatus according to claim 1, wherein the accelerator is a graphics accelerator.
Claim 4
Dependent Claim
70 words
A computing apparatus according to claim 1, further comprising: a writepointer coupled to the accelerator and controlled by the processor, the writepointer being updated by the processor routine to designate posting of a message from the processor to the accelerator via the queue; and a readpointer coupled to the accelerator and controlled by the accelerator, the readpointer being updated by the accelerator dispatcher routine to designate consumption of a message.
Claim 5
Dependent Claim
34 words
A computing apparatus according to claim 3, further comprising: a shadow writepointer stored in a storage coupled local to the processor, the shadow writepointer being updated by the processor routine to shadow the writepointer.
Claim 6
Dependent Claim
22 words
A computing apparatus according to claim 1, wherein the processor routine includes a routine that controls the queue as a circular queue.
Claim 7
Dependent Claim
18 words
A computing apparatus according to claim 1, further comprising: a system bus coupling the processor to the accelerator.
Claim 8
Dependent Claim
31 words
A computing apparatus according to claim 1, wherein the configuration routine includes a routine that configures the queue size according to a message throughput of from the processor to the accelerator.
Claim 9
Dependent Claim
21 words
A computing apparatus according to claim 1, wherein the queue is allocated in an offscreen portion of a video memory storage.
Claim 10
Independent Claim
102 words
A method of communicating messages from a processor to an accelerator using a software queue including: allocating a queue in a central storage that is coupled to the processor and controlled by the processor; establishing mutually exclusive access to the software queue to an application; determining a position in the queue for posting a message from the processor to the accelerator; posting the message to the queue from the processor via a bus without intermediate hardware FIFO buffering; waiting in the accelerator for a message to be posted in the queue; and performing, in the accelerator, the message posted in the queue.
Claim 11
Independent Claim
102 words
A method of communicating messages from a processor to an accelerator using a software queue including: allocating a queue in a central storage that is coupled to the processor and controlled by the processor; establishing mutually exclusive access to the software queue to an application; determining a position in the queue for posting a message from the processor to the accelerator; posting the message to the queue from the processor via a bus without intermediate hardware FIFO buffering; waiting in the accelerator for a message to be posted in the queue; and performing, in the accelerator, the message posted in the queue.
Claim 12
Dependent Claim
35 words
A method according to claim 9, further comprising: writing a message into the queue at a position determined by a writepointer; and consuming a message from the queue at a position determined by a readpointer.
Claim 13
Dependent Claim
14 words
A method according to claim 10, further comprising: shadowing the writepointer in the processor.
Claim 14
Dependent Claim
99 words
A method according to claim 9, wherein determining the position in the queue comprises: comparing a value of a writepointer designating a position in the queue at which a message is posted to a value of a readpointer designating a position in the queue at which a message is consumed; determining whether the queue is full or a queue entry is available on the basis of a result of the comparison; allocating a position in the queue if a queue entry is available; and updating the value of a writepointer in accordance with the allocated position in the queue.
Claim 15
Dependent Claim
41 words
A method according to claim 9, wherein the message posting step comprises: writing a value of a writepointer to a writepointer designating a position in the queue; and writing the message to the queue at the position designated by the writepointer.
Claim 16
Dependent Claim
29 words
A method according to claim 9, wherein waiting for a message to be posted in the queue further comprises: monitoring a writepointer; and waiting until the writepointer changes value.
Claim 17
Dependent Claim
11 words
A method according to claim 9, further comprising: initializing the queue.
Claim 18
Dependent Claim
35 words
A method according to claim 15, wherein initializing the queue further comprises: initializing a thread executing on the accelerator including setting a location of the queue, initializing a readpointer register and initializing a writepointer register.
Claim 19
Dependent Claim
135 words
An article of manufacture comprising: a non-volatile memory; a plurality of instructional sections stored in the non-volatile memory, the instructional sections defining information relating to controlling a software queue for communicating information without intermediate hardware FIFO buffering from a processor to an accelerator; a programmed executable code that controls the software queue and is executable on the processor and on the accelerator, the control programmed executable code further including: a configuration routine allocating a queue within a central storage coupled to and controlled by the processor; a message posting routine executing on the processor and writing a message to the queue without intermediate hardware FIFO buffering; and a message consuming routine executing on the accelerator, reading a message from the queue without intermediate hardware FIFO buffering, and activating the message for performance by the accelerator.
Claim 20
Dependent Claim
135 words
An article of manufacture comprising: a non-volatile memory; a plurality of instructional sections stored in the non-volatile memory, the instructional sections defining information relating to controlling a software queue for communicating information without intermediate hardware FIFO buffering from a processor to an accelerator; a programmed executable code that controls the software queue and is executable on the processor and on the accelerator, the control programmed executable code further including: a configuration routine allocating a queue within a central storage coupled to and controlled by the processor; a message posting routine executing on the processor and writing a message to the queue without intermediate hardware FIFO buffering; and a message consuming routine executing on the accelerator, reading a message from the queue without intermediate hardware FIFO buffering, and activating the message for performance by the accelerator.
Claim 21
Dependent Claim
131 words
A computing apparatus comprising: a processor; an accelerator coupled to the processor; a central storage coupled to the processor without intermediate hardware FIFO buffering and controlled by the processor, the central storage also being coupled to the accelerator without intermediate hardware FIFO buffering; and means for allocating a software queue in the storage; means for establishing mutually exclusive access to the software queue to an application; means for determining a position in the queue for posting a message from the processor to the accelerator; means for posting the message to the queue from the processor via a bus without intermediate hardware FIFO buffering; means for waiting in the accelerator for a message to be posted in the queue; and means for performing, in the accelerator, the message posted in the queue.
Claim 22
Dependent Claim
131 words
A computing apparatus comprising: a processor; an accelerator coupled to the processor; a central storage coupled to the processor without intermediate hardware FIFO buffering and controlled by the processor, the central storage also being coupled to the accelerator without intermediate hardware FIFO buffering; and means for allocating a software queue in the storage; means for establishing mutually exclusive access to the software queue to an application; means for determining a position in the queue for posting a message from the processor to the accelerator; means for posting the message to the queue from the processor via a bus without intermediate hardware FIFO buffering; means for waiting in the accelerator for a message to be posted in the queue; and means for performing, in the accelerator, the message posted in the queue.
Claim 23
Dependent Claim
40 words
A computing apparatus according to claim 18, further comprising: means for writing a message into the queue at a position determined by a writepointer; and means for consuming a message from the queue at a position determined by a readpointer.
Claim 24
Dependent Claim
17 words
A computing apparatus according to claim 18, further comprising: means for shadowing the writepointer in the processor.
Claim 25
Dependent Claim
98 words
A computing apparatus according to claim 18, further comprising: means for comparing a value of a writepointer designating a position in the queue for posting a message to a value of a readpointer designating a position in the queue for consuming a message; means for determining whether the queue is full or a queue entry is available on the basis of a result of the comparison; means for allocating a position in the queue if a queue entry is available; and means for updating the value of a writepointer in accordance with the allocated position in the queue.
Claim 26
Dependent Claim
42 words
A computing apparatus according to claim 18, further comprising: means for writing a value of a writepointer to a writepointer designating a position in the queue; and means for writing the message to the queue at the position designated by the writepointer.
Claim 27
Dependent Claim
37 words
A computing apparatus according to claim 18, wherein the means for waiting for a message to be posted in the queue further comprises: means for monitoring a writepointer; and means for waiting until the writepointer changes value.
Claim 28
Dependent Claim
14 words
A computing apparatus according to claim 18, further comprising: means for initializing the queue.
Claim 29
Dependent Claim
39 words
A computing apparatus according to claim 18, wherein the means for initializing the queue further comprises: means for initializing a thread executing on the accelerator including setting a location of the queue, initializing a readpointer and initializing a writepointer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |