US5948698A
Expired / Lapsed
US
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Manufacturing method of semiconductor device using chemical mechanical polishing
Assignee: Toshiba Corp
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Filing: 1997-10-15
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Granted: 1999-09-07
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Expires: 2017-10-15
Abstract
Abstract A method for fabricating a semiconductor device at low cost is provided in which a mask layer having a very large polishing selection ratio is used as a polishing stop film by forming the polishing stop film in self-alignment. An object layer to be flattened is formed on a substrate. The object layer contains an irregularity. A polishing stop film which is polished at a slower rate and a mask layer which is polished at about the same rate as the object layer are deposited on the object layer. Then, the mask layer on a high level portion of the object layer is removed by chemical-mechanical polishing. The polishing stop film is etched other than under the mask layer, so that the polishing stop film at the high level portion and side wall of the step is removed. Because the polishing stop film at the convex portions (high level portion) is removed by etching utilizing a chemical reaction without using chemical-mechanical polishing, it is possible to select a material for the polishing stop film which is polished at a very slow rate. After that, the mask layer and the object layer at the convex portion are removed by CMP to level off the object layer with the concave portion.
Inventors
- 👤 Masahiro Inohara
- 👤 Tadashi Matsuno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:53
CPC Classifications
H; H10; H10P; H10P95/00; H10P95/06; H10P95/062; H10P52/00; H10P52/40; H10P52/403; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0143; H10W10/10; H10W10/17; H10W20/00; H10W20/01; H10W20/031; H10W20/062; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
121 words
A self-alignment method for manufacturing a semiconductor device having a layer containing at least one irregularity, comprising the steps of: forming a polishing stop film on said layer; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said layer corresponding to said at least one irregularity; removing said polishing stop film on the high level portion of said layer corresponding to said at least one irregularity; polishing the high level portion of the irregularity of said layer corresponding to said at least one irregularity, wherein said polishing stop film has a greater polishing rate than that of said mask layer.
Claim 2
Dependent Claim
121 words
A self-alignment method for manufacturing a semiconductor device having a layer containing at least one irregularity, comprising the steps of: forming a polishing stop film on said layer; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said layer corresponding to said at least one irregularity; removing said polishing stop film on the high level portion of said layer corresponding to said at least one irregularity; polishing the high level portion of the irregularity of said layer corresponding to said at least one irregularity, wherein said polishing stop film has a greater polishing rate than that of said mask layer.
Claim 3
Dependent Claim
20 words
A method for manufacturing a semiconductor device according to claim 1, wherein the polishing steps are performed by chemical-mechanical polishing.
Claim 4
Dependent Claim
24 words
A method for manufacturing a semiconductor device according to claim 1, wherein said first film is removed by isotropic etching in said removing step.
Claim 5
Dependent Claim
27 words
A method for manufacturing a semiconductor device according to claim 1, wherein said first film is removed only on the high level portion in said removing step.
Claim 6
Dependent Claim
36 words
A method for manufacturing a semiconductor device according to claim 1, wherein said first film is removed only on said high level portion, or a sidewall between said high level portion and a low level portion.
Claim 7
Dependent Claim
39 words
A method for manufacturing a semiconductor device according to claim 1, wherein said first film is removed only on said high level portion, or a portion of a side wall between said high level portion and a low portion.
Claim 8
Dependent Claim
31 words
A method for manufacturing a semiconductor device according to claim 1, wherein said first film has a polishing rate which is less than 1/10 of a polishing rate of said layer.
Claim 9
Dependent Claim
31 words
A method for manufacturing a semiconductor device according to claim 1, wherein said first film is selected from a group comprising carbon, Si 3 N 4 , poly-Si and metal silicide.
Claim 10
Dependent Claim
25 words
A method for manufacturing a semiconductor device according to claim 1, further comprising the step of: removing said second film after removing said first film.
Claim 11
Dependent Claim
21 words
A method for manufacturing a semiconductor device according to claim 9, wherein said second film is removed by chemical mechanical polishing.
Claim 12
Dependent Claim
23 words
A method for manufacturing a semiconductor device according to claim 1, wherein said layer is formed by chemical vapor deposition with bias sputtering.
Claim 13
Dependent Claim
23 words
A method for manufacturing a semiconductor device according to claim 1, wherein said second film is formed by chemical vapor deposition with sputtering.
Claim 14
Dependent Claim
18 words
A method for manufacturing a semiconductor device according to claim 1, wherein said layer is a metal layer.
Claim 15
Dependent Claim
32 words
A method for manufacturing a semiconductor device according to claim 13, wherein said metal is selected from a group comprising Au, Al, Cu, an alloy of Cu and an alloy of Al.
Claim 16
Dependent Claim
18 words
A method for manufacturing a semiconductor device according to claim 1, wherein said layer is an insulating layer.
Claim 17
Dependent Claim
19 words
A method for manufacturing a semiconductor device according to claim 15, wherein said insulating layer is SiO 2 layer.
Claim 18
Dependent Claim
110 words
A self-alignment method for manufacturing a semiconductor device having a layer containing at least one irregularity, comprising the steps of: forming a polishing stop film on said layer; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said layer corresponding to said at least one irregularity; removing said polishing stop film on the high level portion of said layer corresponding to said at least one irregularity; and polishing a surface of said layer, wherein said polishing stop film has a greater polishing rate than that of said mask layer.
Claim 19
Dependent Claim
110 words
A self-alignment method for manufacturing a semiconductor device having a layer containing at least one irregularity, comprising the steps of: forming a polishing stop film on said layer; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said layer corresponding to said at least one irregularity; removing said polishing stop film on the high level portion of said layer corresponding to said at least one irregularity; and polishing a surface of said layer, wherein said polishing stop film has a greater polishing rate than that of said mask layer.
Claim 20
Dependent Claim
88 words
A self-alignment method for manufacturing a semiconductor device having a trench on a semiconductor substrate, comprising the steps of: forming a polishing stop film on a layer to be flattened, said layer having at least one irregularity; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on high level portion of said layer; removing said polishing stop film on said high level portion of said layer; and polishing a surface of said layer.
Claim 21
Dependent Claim
88 words
A self-alignment method for manufacturing a semiconductor device having a trench on a semiconductor substrate, comprising the steps of: forming a polishing stop film on a layer to be flattened, said layer having at least one irregularity; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on high level portion of said layer; removing said polishing stop film on said high level portion of said layer; and polishing a surface of said layer.
Claim 22
Dependent Claim
91 words
A self-alignment method for manufacturing a semiconductor device having a trench on a semiconductor substrate, comprising the steps of: forming a polishing stop film on a layer to be flattened, said layer having at least one irregularity; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said layer; removing said polishing stop film on said high level portion of said layer; and polishing a high level portion of said layer.
Claim 23
Dependent Claim
91 words
A self-alignment method for manufacturing a semiconductor device having a trench on a semiconductor substrate, comprising the steps of: forming a polishing stop film on a layer to be flattened, said layer having at least one irregularity; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said layer; removing said polishing stop film on said high level portion of said layer; and polishing a high level portion of said layer.
Claim 24
Dependent Claim
101 words
A self-alignment method for manufacturing a semiconductor device having a semiconductor element region on a semiconductor substrate, comprising the steps of: forming a trench surrounding said semiconductor element region; forming an insulating film on said substrate; forming a polishing stop film on said insulating film; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said insulating film; removing said polishing stop film on said high-level portion of said insulating film; and polishing said high level portion of said insulating film.
Claim 25
Dependent Claim
101 words
A self-alignment method for manufacturing a semiconductor device having a semiconductor element region on a semiconductor substrate, comprising the steps of: forming a trench surrounding said semiconductor element region; forming an insulating film on said substrate; forming a polishing stop film on said insulating film; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said insulating film; removing said polishing stop film on said high-level portion of said insulating film; and polishing said high level portion of said insulating film.
Claim 26
Dependent Claim
100 words
A self-alignment method for manufacturing a semiconductor device having a semiconductor element region on a semiconductor substrate, comprising the steps of: forming a trench surrounding said semiconductor element region; forming an insulating film on said substrate; forming a polishing stop film on said insulating film; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said insulating film; removing said polishing stop film on said high level portion of said insulating film; and polishing a surface of said insulating film.
Claim 27
Dependent Claim
100 words
A self-alignment method for manufacturing a semiconductor device having a semiconductor element region on a semiconductor substrate, comprising the steps of: forming a trench surrounding said semiconductor element region; forming an insulating film on said substrate; forming a polishing stop film on said insulating film; forming a mask layer on said polishing stop film; polishing a whole surface of said semiconductor device in order to polish said mask layer on a high level portion of said insulating film; removing said polishing stop film on said high level portion of said insulating film; and polishing a surface of said insulating film.
Claim 28
Dependent Claim
49 words
A self-alignment method for manufacturing a semiconductor device comprising the steps of: forming a film to be polished; forming a polishing stop film; forming a mask layer; implementing a first polishing of a whole surface of said semiconductor device; etching said polishing stop film; and implementing a second polishing.
Claim 29
Dependent Claim
49 words
A self-alignment method for manufacturing a semiconductor device comprising the steps of: forming a film to be polished; forming a polishing stop film; forming a mask layer; implementing a first polishing of a whole surface of said semiconductor device; etching said polishing stop film; and implementing a second polishing.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-09-06 | 2003-03-08 | 2003-09-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-09-06 | 2007-03-08 | 2007-09-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-09-06 | 2011-03-08 | 2011-09-07 | $7700.00 | Window Closed / Lapsed |