System for assigning a received data packet to a data communications channel by comparing portion of data packet to predetermined match set to check correspondence for directing channel select signal

Claim 3

The method of claim 1, wherein said data packet associates with a plurality of similar data packets, said plurality of data packets likewise having portions of respected data packets compared to respective match data sets for directing a plurality of respective channel select signals to at least one data communications channel, said method further comprising the steps of: receiving said channel select signal and said plurality of respective channel select signals in a priority encoder circuit; directing at least one of said channel select signal and said plurality of respective channel select signals to at least one data communications channel according to a predetermined priority data value associated with the combination of said channel select signal and said plurality of respective channel select signals.

Claim 4

The method of claim 2, further comprising the step of combining said channel select signal and said plurality of respective channel select signals for generating a logically 0Red comparator match signal to receiver control logic associated with said data communications channel.

Claim 5

The method of claim 1, wherein said comparing step further comprises the step of comparing a word 0 field select register content with a word 0 compare value register contents.

Claim 6

The method of claim 1, wherein said comparing step further comprise the step of comparing a word 1 field select register contents with a word 1 compare value register contents.

Claim 7

The method of claim 1, wherein said comparing step further comprises the step of comparing said portion of said data packet comprising word 0 and word 1 of an incoming data packet to a match data set.

Claim 8

The method of claim 1, wherein said comparing step further comprises the step further comprises the step of comparing said portion of said data packet to a match data set, said match data set comprising a word 0 and a word 1 expected value.

Claim 9

A DMA channel receive packet comparator circuit for assigning a data packet to a data communications channel, comprising: a receive comparator for receiving at least a portion of a data packet in a data packet comparison circuit, comparison circuitry associated with said receive comparator for comparing at least said portion of said data packet to a predetermined match data set, said predetermined match data set comprising programmably varying data fields defining at least one expected data word corresponding to at least one direct memory access channel; and directing circuitry for directing a channel select signal to said at least one direct memory access channel for in the event of a predetermined correspondence between said at least said portion and said match data set.

Claim 10

A DMA channel receive packet comparator circuit for assigning a data packet to a data communications channel, comprising: a receive comparator for receiving at least a portion of a data packet in a data packet comparison circuit, comparison circuitry associated with said receive comparator for comparing at least said portion of said data packet to a predetermined match data set, said predetermined match data set comprising programmably varying data fields defining at least one expected data word corresponding to at least one direct memory access channel; and directing circuitry for directing a channel select signal to said at least one direct memory access channel for in the event of a predetermined correspondence between said at least said portion and said match data set.

Claim 11

The direct memory access channel receive packet comparator circuit of claim 8, wherein said data packet associates with a plurality of similar data packets, said plurality of data packets likewise having portions of respected data packets compared to respective match data sets for directing a plurality of respective channel select signals to at least one data communications channel, said DMA channel receive packet comparator circuit further comprising: a priority encoder for receiving said channel select signal and said plurality of respective channel select signals; directing circuitry associated with said priority encoder for directing at least one of said channel select signal and said plurality of respective channel select signals to at least one direct memory access channel according to a predetermined priority data value associated with the combination of said channel select signal and said plurality of respective channel select signals.

Claim 12

The DMA channel receive packet comparator circuit of claim 9, further comprising circuitry for combining said channel select signal and said plurality of respective channel select signals for generating a logically 0R-ed comparator match signal to receiver control logic associated with said data communications channel.

Claim 13

The DMA channel receive packet comparator circuit of claim 8 wherein said comparing circuitry further comprises circuitry for comparing a word 0 field select register content with a word 0 compare value register contents.

Claim 14

The DMA channel receive packet comparator circuit of claim 9, wherein said comparing circuitry further comprises circuitry for comparing a word 1 field select register contents with a word 1 compare value register contents.

Claim 15

The DMA channel receive packet comparator circuit of claim 8, wherein said comparing circuitry for comparing said portion of said data packet comprising word 0 and word 1 of an incoming data packet to a match data set.

Claim 16

The DMA channel receive packet comparator circuit of claim 8, wherein said comparing circuitry further comprises circuitry for comparing said portion of said data packet to a match data set, said match data set comprising a word 0 and a word 1 expected value.

Claim 17

A personal computer system, comprising: at least one peripheral employing a data packet transfer bus; a computer, said computer comprising: a host cpu comprising a PCI bus; and a PCI-interface device for providing an interface between said PCI bus and said peripheral, said PCI-interface device comprising a DMA channel receive packet comparator circuit for assigning a data packet to a DMA channel, comprising: a receive comparator for receiving at least a portion of a data packet in a data packet comparison circuit; comparison circuitry associated with said receive comparator for comparing at least said portion of said data packet to a predetermined match data set, said match data set comprising programmably varying data fields corresponding to at least one data communications channel; and directing circuitry for directing a channel select signal to said at least one DMA channel in the event of a predetermined correspondence between said at least said portion and said match data set.

Claim 18

A personal computer system, comprising: at least one peripheral employing a data packet transfer bus; a computer, said computer comprising: a host cpu comprising a PCI bus; and a PCI-interface device for providing an interface between said PCI bus and said peripheral, said PCI-interface device comprising a DMA channel receive packet comparator circuit for assigning a data packet to a DMA channel, comprising: a receive comparator for receiving at least a portion of a data packet in a data packet comparison circuit; comparison circuitry associated with said receive comparator for comparing at least said portion of said data packet to a predetermined match data set, said match data set comprising programmably varying data fields corresponding to at least one data communications channel; and directing circuitry for directing a channel select signal to said at least one DMA channel in the event of a predetermined correspondence between said at least said portion and said match data set.

Claim 19

The personal computer system of claim 15, wherein said DMA channel receive packet comparator further comprises circuitry for combining said channel select signal and said plurality of respective channel select signals for generating a logically 0R-ed comparator match signal to receiver control logic associated with said data communications channel.

Claim 20

The personal computer system of claim 15, wherein said DMA channel receive packet comparator comparing circuitry further comprises circuitry for comparing a word 0 field select register content with a word 0 compare value register contents.

Claim 21

The personal computer system of claim 15, wherein said DMA channel receive packet comparator comparing circuitry further comprises circuitry for comparing a word 1 field select register contents with a word 1 compare value register contents.

Claim 22

The personal computer system of claim 15, wherein said comparing circuitry for comparing said portion of said data packet comprising word 0 and word 1 of an incoming data packet to a match data set.

Claim 23

The personal computer system of claim 15, wherein said comparing circuitry further comprises circuitry for comparing said portion of said data packet to a match data set, said match data set comprising a word 0 and a word 1 expected value.