Patent US5944837A successfully refreshed from Google Patents.
US5944837A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Controlling flash memory program and erase pulses
Assignee: Intel Corp
•
Filing: 1997-08-18
•
Granted: 1999-08-31
•
Expires: 2017-08-18
Abstract
Abstract An operation control method and apparatus are described. The apparatus includes a timer circuit, a blocking circuit and a control circuit. The timer circuit provides a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal. The blocking circuit receives the done signal and provides the done signal as output if the done signal is not blocked when received. The control circuit receives a begin signal indicating that the operation is to be performed and a limit signal to indicate whether or not a condition exists that would prevent the operation from being completed in a single step. If the limit signal indicates the operation can be completed in the single step, the control circuit starts the timing circuit and controls performance of the single step until the done signal is received. If the limit signal indicates the operation cannot be completed in the single step, the control circuit divides the single step into at least two sub-steps, during each sub-step, the control circuit starts the timing circuit and controls performance of the sub-step until the done signal is received. The control circuit blocks output of the done signal from the blocking circuit during each sub-step until a final sub-step. For one embodiment, the operation to be performed is an erase operation specified by a write state machine that specifies an erase block to be erased within a flash memory. Alternately, the operation to be performed is a program operation specified by a write state machine that specifies data to be programmed within a flash memory.
Inventors
- 👤 Sanjay S. Talreja
- 👤 Rodney R. Rozman
- 👤 Mickey Lee Fandrich
- 👤 Bharat Pathak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:08
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/30
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
194 words
An operation control apparatus comprising: a timer circuit adapted to provide a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal; a blocking circuit adapted to receive the done signal and to provide the done signal as output if the done signal is not blocked when received; a control circuit adapted to receive a begin signal and a limit signal, the begin signal indicating that the operation is to be performed, the limit signal indicating whether a condition exists that would prevent the operation from being completed in a single step; if the limit signal indicates the operation can be completed in the single step, the control circuit starting the timing circuit and controlling performance of the single step until the done signal is received; if the limit signal indicates the operation cannot be completed in the single step, the control circuit dividing the single step into at least two sub-steps, during each sub-step, the control circuit starting the timing circuit and controlling performance of the sub-step until the done signal is received, the control circuit blocking the done signal during each sub-step until a final sub-step.
Claim 2
Dependent Claim
194 words
An operation control apparatus comprising: a timer circuit adapted to provide a done signal upon completion of timing a predetermined elapsed time interval initiated by a start signal; a blocking circuit adapted to receive the done signal and to provide the done signal as output if the done signal is not blocked when received; a control circuit adapted to receive a begin signal and a limit signal, the begin signal indicating that the operation is to be performed, the limit signal indicating whether a condition exists that would prevent the operation from being completed in a single step; if the limit signal indicates the operation can be completed in the single step, the control circuit starting the timing circuit and controlling performance of the single step until the done signal is received; if the limit signal indicates the operation cannot be completed in the single step, the control circuit dividing the single step into at least two sub-steps, during each sub-step, the control circuit starting the timing circuit and controlling performance of the sub-step until the done signal is received, the control circuit blocking the done signal during each sub-step until a final sub-step.
Claim 3
Dependent Claim
27 words
The apparatus of claim 1 wherein the operation to be performed is an erase operation that specifies an erase block to be erased within a flash memory.
Claim 4
Dependent Claim
35 words
The apparatus of claim 2 wherein the condition that exists that would prevent the erase block operation from being completed in a single step is insufficient erase current available to erase the entire erase block.
Claim 5
Dependent Claim
24 words
The apparatus of claim 3 wherein the single step is that of applying an erase pulse to the entire erase block to be erased.
Claim 6
Dependent Claim
48 words
The apparatus of claim 4 wherein if there is insufficient erase current available to erase the entire erase block using one erase pulse, the erase block is divided into sub-blocks and the erase pulse is supplied to a different one of the sub-blocks during each of the sub-steps.
Claim 7
Dependent Claim
25 words
The apparatus of claim 1 wherein the operation to be performed is a program operation that specifies data to be programmed within a flash memory.
Claim 8
Dependent Claim
13 words
The apparatus of claim 6 wherein a word of the data is specified.
Claim 9
Dependent Claim
37 words
The apparatus of claim 7 wherein the condition that exists that would prevent the program operation from being completed in a single step is insufficient program current available to program the entire word of data at once.
Claim 10
Dependent Claim
28 words
The apparatus of claim 8 wherein the single step is that of applying a program pulse to program the entire word of data to be programmed at once.
Claim 11
Dependent Claim
63 words
The apparatus of claim 9 wherein if there is insufficient program current available to program the entire word of data using one program pulse, the word of data to program is divided into sub-portions, a different one of the sub-portions is used to form a masked word during each of the sub-steps and the program pulse is supplied during each of the sub-steps.
Claim 12
Dependent Claim
48 words
The apparatus of claim 10 wherein the masked word to program during each of the sub-steps is formed by setting each bit of the word to program to one if the bit of the word to program does not belong to the sub-portion being programmed during the sub-step.
Claim 13
Dependent Claim
36 words
The apparatus of claim 11 wherein the program current can program at most N zeros at a time and the sub-portions are formed using no more than N bits of the word of data each sub-step.
Claim 14
Dependent Claim
39 words
The apparatus of claim 12 wherein the program current can program at most N zeros at a time and the sub-portions are formed so that at most N zeros of the word of data are programmed during each sub-step.
Claim 15
Dependent Claim
33 words
The apparatus of claim 1 wherein the begin signal is received from a state machine and the done signal is provided to the state machine if provided as output from the blocking circuit.
Claim 16
Dependent Claim
18 words
The apparatus of claim 14 wherein the state machine is a write state machine for a flash memory.
Claim 17
Dependent Claim
14 words
The apparatus of claim 14 wherein the state machine is a programmable logic array.
Claim 18
Dependent Claim
20 words
The apparatus of claim 14 wherein the state machine is a microprocessor operating under the control of a control program.
Claim 19
Dependent Claim
99 words
An operation control method comprising the steps of: receiving an indication that an operation is to be performed; determining whether a condition exists that would prevent the operation from being completed in a single step; if the operation can be completed in the single step, performing the single step; if the operation cannot be completed in the single step, dividing the single step into at least two sub-steps and performing each of the sub-steps until the operation has been performed; and generating an indication that the operation has been performed when the operation to be performed has been completed.
Claim 20
Dependent Claim
99 words
An operation control method comprising the steps of: receiving an indication that an operation is to be performed; determining whether a condition exists that would prevent the operation from being completed in a single step; if the operation can be completed in the single step, performing the single step; if the operation cannot be completed in the single step, dividing the single step into at least two sub-steps and performing each of the sub-steps until the operation has been performed; and generating an indication that the operation has been performed when the operation to be performed has been completed.
Claim 21
Dependent Claim
27 words
The method of claim 18 wherein the operation to be performed is an erase operation that specifies an erase block to be erased within a flash memory.
Claim 22
Dependent Claim
35 words
The method of claim 19 wherein the condition that exists that would prevent the erase block operation from being completed in a single step is insufficient erase current available to erase the entire erase block.
Claim 23
Dependent Claim
24 words
The method of claim 20 wherein the single step is that of applying an erase pulse to the entire erase block to be erased.
Claim 24
Dependent Claim
48 words
The method of claim 21 wherein if there is insufficient erase current available to erase the entire erase block using one erase pulse, the erase block is divide into sub-blocks and the erase pulse is supplied to a different one of the sub-blocks during each of the sub-steps.
Claim 25
Dependent Claim
25 words
The method of claim 18 wherein the operation to be performed is a program operation that specifies data to be programmed within a flash memory.
Claim 26
Dependent Claim
20 words
The method of claim 23 wherein a word of the data is specified to be programmed during the program operation.
Claim 27
Dependent Claim
37 words
The method of claim 24 wherein the condition that exists that would prevent the program operation from being completed in a single step is insufficient program current available to program the entire word of data at once.
Claim 28
Dependent Claim
28 words
The method of claim 25 wherein the single step is that of applying a program pulse to program the entire word of data to be programmed at once.
Claim 29
Dependent Claim
63 words
The method of claim 26 wherein if there is insufficient program current available to program the entire word of data using one program pulse, the word of data to program is divided into sub-portions, a different one of the sub-portions is used to form a masked word during each of the sub-steps and the program pulse is supplied during each of the sub-steps.
Claim 30
Dependent Claim
48 words
The method of claim 27 wherein the masked word to program during each of the sub-steps is formed by setting each bit of the word to program to one if the bit of the word to program does not belong to the sub-portion being programmed during that sub-step.
Claim 31
Dependent Claim
36 words
The method of claim 28 wherein the program current can program at most N zeros at a time and the sub-portions are formed using no more than N bits of the word of data each sub-step.
Claim 32
Dependent Claim
39 words
The method of claim 29 wherein the program current can program at most N zeros at a time and the sub-portions are formed so that at most N zeros of the word of data are programmed during each sub-step.
Claim 33
Dependent Claim
35 words
The method of claim 18 wherein the indication that the operation to be performed is received from a state machine and the indication that the operation has been performed is provided to the state machine.
Claim 34
Dependent Claim
18 words
The method of claim 31 wherein the state machine is a write state machine for a flash memory.
Claim 35
Dependent Claim
14 words
The method of claim 31 wherein the state machine is a programmable logic array.
Claim 36
Dependent Claim
20 words
The method of claim 31 wherein the state machine is a microprocessor operating under the control of a control program.
Claim 37
Dependent Claim
94 words
Method comprising the steps of: receiving an erase command for a portion of a memory, and, in response to the erase command: (1) dividing an erase operation into sequential erase operations performed on two or more respective subsections of the portion of the memory if an amount of current available for erasure is below a predetermined amount; and; (2) performing an erase operation on the portion of the memory without dividing the portion of the memory with respect to erase operations if the amount of current available for erasure is above the predetermined amount.
Claim 38
Dependent Claim
94 words
Method comprising the steps of: receiving an erase command for a portion of a memory, and, in response to the erase command: (1) dividing an erase operation into sequential erase operations performed on two or more respective subsections of the portion of the memory if an amount of current available for erasure is below a predetermined amount; and; (2) performing an erase operation on the portion of the memory without dividing the portion of the memory with respect to erase operations if the amount of current available for erasure is above the predetermined amount.
Claim 39
Dependent Claim
19 words
The method of claim 35, wherein the erase command is received from a write state machine on the memory.
Claim 40
Dependent Claim
16 words
The apparatus of claim 35, wherein the portion of the memory is a block of memory.
Claim 41
Independent Claim
120 words
A method comprising the steps of: (1) generating an erase command for a portion of a memory array, wherein the erase command is not dependent upon an amount of current available for erasure; (2) receiving the erase command, and, in response to the erase command: (a) dividing an erase operation into sequential erase operations performed on two or more respective subsections of the portion of the memory array if the amount of current available for erasure is below a predetermined amount, and; (b) performing an erase operation on the portion of the memory array without dividing the portion of the memory array with respect to erase operations if the amount of current available for erasure is above the predetermined amount.
Claim 42
Independent Claim
120 words
A method comprising the steps of: (1) generating an erase command for a portion of a memory array, wherein the erase command is not dependent upon an amount of current available for erasure; (2) receiving the erase command, and, in response to the erase command: (a) dividing an erase operation into sequential erase operations performed on two or more respective subsections of the portion of the memory array if the amount of current available for erasure is below a predetermined amount, and; (b) performing an erase operation on the portion of the memory array without dividing the portion of the memory array with respect to erase operations if the amount of current available for erasure is above the predetermined amount.
Claim 43
Independent Claim
91 words
A method comprising the steps of: receiving a program command for a portion of memory, and, in response to the program command: (1) dividing a program operation into sequential program operations performed on two or more respective subsections of the portion of memory if an amount of current available for programming is below a predetermined amount; and, (2) performing a program operation on the portion of memory without dividing the portion of memory with respect to program operations if the amount of current available for programming is above the predetermined amount.
Claim 44
Independent Claim
91 words
A method comprising the steps of: receiving a program command for a portion of memory, and, in response to the program command: (1) dividing a program operation into sequential program operations performed on two or more respective subsections of the portion of memory if an amount of current available for programming is below a predetermined amount; and, (2) performing a program operation on the portion of memory without dividing the portion of memory with respect to program operations if the amount of current available for programming is above the predetermined amount.
Claim 45
Independent Claim
96 words
A method comprising the steps of: receiving a program command for a portion of memory, and, in response to the program command: (1) dividing a program operation into sequential program operations performed by applying two or more different bit patterns to the portion of memory if an amount of current available for programming is below a predetermined amount, and, (2) performing a program operation on the portion of memory without sequentially applying two or more different bit patterns to the portion of memory if the amount of current available for programming is above a predetermined amount.
Claim 46
Independent Claim
96 words
A method comprising the steps of: receiving a program command for a portion of memory, and, in response to the program command: (1) dividing a program operation into sequential program operations performed by applying two or more different bit patterns to the portion of memory if an amount of current available for programming is below a predetermined amount, and, (2) performing a program operation on the portion of memory without sequentially applying two or more different bit patterns to the portion of memory if the amount of current available for programming is above a predetermined amount.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-30 | 2003-03-01 | 2003-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-30 | 2007-03-01 | 2007-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-30 | 2011-03-01 | 2011-08-31 | $7700.00 | Window Closed / Lapsed |