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US5944800A
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Direct memory access unit having a definable plurality of transfer channels
Assignee: Infineon Technologies AG
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Filing: 1997-09-12
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Granted: 1999-08-31
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Expires: 2017-09-12
Abstract
Abstract Th present invention relates to a DMA-controller having a definable plurality of transfer channels. According to the present invention such a unit comprises a data processing unit with a bus interface unit being coupled with a bus for transferring data. The data processing unit executes a data transfer on said bus dependent on programmable parameters. It further comprises a parameter memory storing those parameters for each transfer channel, whereby the parameter memory provides a first memory area which stores for each defined transfer channel a word comprising a vector address to a second memory area comprising specific parameters for said transfer channel.
Inventors
- 👤 Karl-Heinz Mattheis
- 👤 Peter Rohm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 13:49
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
102 words
Direct memory access unit having a definable plurality of transfer channels comprising: a data processing unit having a bus interface unit being coupled with a bus for transferring data, said data processing unit executing a data transfer on said bus dependent on programmable parameters; and a parameter memory storing said parameters for each transfer channel, whereby said parameter memory provides a first memory area storing for each defined transfer channel data comprising a vector address to a second memory area comprising specific parameters for said transfer channel and a transfer instruction defining the number of parameters stored in said second memory area.
Claim 2
Dependent Claim
102 words
Direct memory access unit having a definable plurality of transfer channels comprising: a data processing unit having a bus interface unit being coupled with a bus for transferring data, said data processing unit executing a data transfer on said bus dependent on programmable parameters; and a parameter memory storing said parameters for each transfer channel, whereby said parameter memory provides a first memory area storing for each defined transfer channel data comprising a vector address to a second memory area comprising specific parameters for said transfer channel and a transfer instruction defining the number of parameters stored in said second memory area.
Claim 3
Dependent Claim
31 words
Unit as in claim 1, wherein said data processing unit comprises a data manipulating unit which upon said programmed parameters is able to alter said data being transferred on said bus.
Claim 4
Dependent Claim
13 words
Unit as in claim 2, wherein said manipulating unit comprises an arithmetic operator.
Claim 5
Dependent Claim
13 words
Unit as in claim 2, wherein said manipulating unit comprises a logical operator.
Claim 6
Dependent Claim
13 words
Unit as in claim 2, wherein said manipulating unit comprises a compare unit.
Claim 7
Dependent Claim
22 words
Unit as in claim 1, wherein said parameters comprise a source pointer, a destination pointer, a transfer counter, and a channel command.
Claim 8
Dependent Claim
14 words
Unit as in claim 6, wherein said parameters further comprise a data manipulate register.
Claim 9
Dependent Claim
14 words
Unit as in claim 7, wherein said parameters further comprise a second source pointer.
Claim 10
Dependent Claim
14 words
Unit as in claim 1, wherein said parameter memory is a dual port memory.
Claim 11
Dependent Claim
137 words
Direct memory access unit having a definable plurality of transfer channels comprising: a code memory storing instructions, a data processing unit connected to said code memory having a bus interface unit being coupled with a bus for transferring data, said data processing unit executing a data transfer on said bus by executing a program stored in said code memory, and which is dependent on programmable parameters, wherein said parameters comprise a source pointer, a destination pointer, a transfer counter, and a channel command; and a parameter memory storing said parameters for each transfer channel, whereby said code memory provides a first memory area and a second memory area, said first memory area storing for each defined transfer channel an entry point address in said second memory area, said second memory area containing at least one program sequence.
Claim 12
Dependent Claim
137 words
Direct memory access unit having a definable plurality of transfer channels comprising: a code memory storing instructions, a data processing unit connected to said code memory having a bus interface unit being coupled with a bus for transferring data, said data processing unit executing a data transfer on said bus by executing a program stored in said code memory, and which is dependent on programmable parameters, wherein said parameters comprise a source pointer, a destination pointer, a transfer counter, and a channel command; and a parameter memory storing said parameters for each transfer channel, whereby said code memory provides a first memory area and a second memory area, said first memory area storing for each defined transfer channel an entry point address in said second memory area, said second memory area containing at least one program sequence.
Claim 13
Dependent Claim
41 words
Direct memory access unit as in claim 10, wherein said code memory provides a third memory area storing for each defined transfer channel a word comprising a vector address to a fourth memory area comprising specific parameters for said transfer channel.
Claim 14
Dependent Claim
16 words
Unit as in claim 11, wherein said fourth memory area is located in said code memory.
Claim 15
Dependent Claim
16 words
Unit as in claim 11, wherein said fourth memory area is located in said parameter memory.
Claim 16
Dependent Claim
14 words
Unit as in claim 10, wherein said code memory is connected to said bus.
Claim 17
Dependent Claim
15 words
Unit as in claim 10, wherein said code memory is a non volatile flash memory.
Claim 18
Dependent Claim
31 words
Unit as in claim 10, wherein said data processing unit comprises a data manipulating unit which upon said programmed parameters is able to alter said data being transferred on said bus.
Claim 19
Dependent Claim
13 words
Unit as in claim 16, wherein said manipulating unit comprises an arithmetic operator.
Claim 20
Dependent Claim
13 words
Unit as in claim 16, wherein said manipulating unit comprises a logical operator.
Claim 21
Dependent Claim
13 words
Unit as in claim 16, wherein said manipulating unit comprises a compare unit.
Claim 22
Dependent Claim
14 words
Unit as in claim 10, wherein said parameters further comprise a data manipulate register.
Claim 23
Dependent Claim
14 words
Unit as in claim 10, wherein said parameters further comprise a second source pointer.
Claim 24
Dependent Claim
14 words
Unit as in claim 10, wherein said parameter memory is a dual port memory.
References Cited (Backward Citations)
US4797809A
Cited
US4751634A
Cited
US4896261A
Cited
US5179663A
Cited
US5212795A
Cited
US5297242A
Cited
US5644754A
Cited
US5655151A
Cited
US5809335A
Cited
US5613162A
Cited
US5619727A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-30 | 2003-03-01 | 2003-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-30 | 2007-03-01 | 2007-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-30 | 2011-03-01 | 2011-08-31 | $7700.00 | Window Closed / Lapsed |