Patent US5943613A successfully refreshed from Google Patents.
US5943613A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for reducing standby current in communications equipment
Assignee: Telefonaktiebolaget LM Ericsson AB
•
Filing: 1996-11-07
•
Granted: 1999-08-24
•
Expires: 2016-11-07
Abstract
Abstract A method and apparatus for reducing power consumption in a communication device. In a standby mode, a relatively high power clock with a high degree of accuracy is powered down and a lower power, low frequency clock is used to maintain system synchronization. Synchronization means are provided to improve the accuracy of the low frequency clock during the standby mode.
Inventors
- 👤 Heino Jean Wendelrup
- 👤 Bjorn Martin Gunnar Lindquist
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:04
CPC Classifications
H; H04; H04W; H04W52/00; H04W52/02; H04W52/0209; H04W52/0261; H04W52/0287; H04W52/029; H04B; H04B1/00; H04B1/06; H04B1/16; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/0802; H03L7/14; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H03L7/1976; H03L2207/00; H03L2207/08; H04W52/0293; Y; Y02; Y02D; Y02D30/00; Y02D30/70
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
139 words
A method for reducing power consumption in a telecommunications device, comprising the steps of: powering down a first system clock contained in the telecommunications device during a predetermined period of time; and powering up a second system clock contained in the telecommunications device during the predetermined period of time, the second system clock drawing less current than the first system clock, and the second system clock including synchronization means for substantially synchronizing the second system clock with the first system clock during the predetermined period of time, wherein the synchronization means includes first and second counters for counting the first and second system clocks, respectively, logic circuitry to substantially synchronize the second system clock with the first system clock, and a feedback loop connected between an output of the logic circuitry and an input to the second system clock.
Claim 2
Independent Claim
139 words
A method for reducing power consumption in a telecommunications device, comprising the steps of: powering down a first system clock contained in the telecommunications device during a predetermined period of time; and powering up a second system clock contained in the telecommunications device during the predetermined period of time, the second system clock drawing less current than the first system clock, and the second system clock including synchronization means for substantially synchronizing the second system clock with the first system clock during the predetermined period of time, wherein the synchronization means includes first and second counters for counting the first and second system clocks, respectively, logic circuitry to substantially synchronize the second system clock with the first system clock, and a feedback loop connected between an output of the logic circuitry and an input to the second system clock.
Claim 3
Dependent Claim
15 words
The method of claim 1, wherein the feedback loop includes a digital to analog converter.
Claim 4
Independent Claim
177 words
A method for reducing power consumption in a telecommunications device, comprising the steps of: powering down a first system clock contained in the telecommunications device during a predetermined period of time; and powering up a second system clock contained in the telecommunications device during the predetermined period of time, the second system clock drawing less current than the first system clock, and the second system clock including synchronization means for substantially synchronizing the second system clock with the first system clock during the predetermined period of time, wherein the synchronization means includes first and second counters for counting the first and second system clocks, respectively, a phase detector for detecting a phase difference between outputs of the first and second counters, a charge pump for converting the phase difference to charge pulses and supplying the charge pulses to the second system clock, and wherein the synchronization means further includes a modulator connected between an output of the first counter and an input of the first counter, the modulator digitally controlling a division ratio of the first counter.
Claim 5
Independent Claim
177 words
A method for reducing power consumption in a telecommunications device, comprising the steps of: powering down a first system clock contained in the telecommunications device during a predetermined period of time; and powering up a second system clock contained in the telecommunications device during the predetermined period of time, the second system clock drawing less current than the first system clock, and the second system clock including synchronization means for substantially synchronizing the second system clock with the first system clock during the predetermined period of time, wherein the synchronization means includes first and second counters for counting the first and second system clocks, respectively, a phase detector for detecting a phase difference between outputs of the first and second counters, a charge pump for converting the phase difference to charge pulses and supplying the charge pulses to the second system clock, and wherein the synchronization means further includes a modulator connected between an output of the first counter and an input of the first counter, the modulator digitally controlling a division ratio of the first counter.
Claim 6
Dependent Claim
21 words
The method of claim 3, wherein the modulator is a sigma delta modulator which receives control information from an external source.
Claim 7
Dependent Claim
13 words
The method of claim 3, wherein the modulator receives no external control information.
Claim 8
Dependent Claim
124 words
A synchronization circuit in a telecommunications device, comprising: a first system clock which operates at a first power level; and a second system clock which operates at a second power level lower than the first power level, the second system clock including synchronization means for substantially synchronizing the second system clock to the first system clock during a predetermined period of time in which the first system clock is powered down, wherein the synchronization means includes first and second counters for counting the first and second system clocks, respectively, and logic circuitry to substantially synchronize the second system clock with the first system clock, and a feedback loop connected between an output of the logic circuitry and an input to the second system clock.
Claim 9
Dependent Claim
124 words
A synchronization circuit in a telecommunications device, comprising: a first system clock which operates at a first power level; and a second system clock which operates at a second power level lower than the first power level, the second system clock including synchronization means for substantially synchronizing the second system clock to the first system clock during a predetermined period of time in which the first system clock is powered down, wherein the synchronization means includes first and second counters for counting the first and second system clocks, respectively, and logic circuitry to substantially synchronize the second system clock with the first system clock, and a feedback loop connected between an output of the logic circuitry and an input to the second system clock.
Claim 10
Dependent Claim
15 words
The circuit of claim 6, wherein the feedback loop includes a digital to analog converter.
Claim 11
Dependent Claim
161 words
A synchronization circuit in a telecommunications device, comprising: a first system clock which operates at a first power level; and a second system clock which operate at a second power level lower than the first power level, the second system clock including synchronization means for substantially synchronizing the second system clock to the first system clock during a predetermined period of time in which the first system clock is powered down, wherein the synchronization means includes first and second counters for counting the first and second system clock, respectively, a phase detector for detecting a phase difference between outputs of the first and second counters, a charge pump for converting the phase difference to charge pulses and supplying the charge pulses to the second system clock, and wherein the synchronization means further includes a modulator connected between an output of the first counter and an input of the first counter, the modulator digitally controlling a division ratio of the first counter.
Claim 12
Dependent Claim
161 words
A synchronization circuit in a telecommunications device, comprising: a first system clock which operates at a first power level; and a second system clock which operate at a second power level lower than the first power level, the second system clock including synchronization means for substantially synchronizing the second system clock to the first system clock during a predetermined period of time in which the first system clock is powered down, wherein the synchronization means includes first and second counters for counting the first and second system clock, respectively, a phase detector for detecting a phase difference between outputs of the first and second counters, a charge pump for converting the phase difference to charge pulses and supplying the charge pulses to the second system clock, and wherein the synchronization means further includes a modulator connected between an output of the first counter and an input of the first counter, the modulator digitally controlling a division ratio of the first counter.
Claim 13
Dependent Claim
21 words
The circuit of claim 8, wherein the modulator is a sigma delta modulator which receives control information from an external source.
Claim 14
Dependent Claim
13 words
The circuit of claim 8, wherein the modulator receives no external control information.
References Cited (Backward Citations)
US5187471A
Cited
WO1991007824A1
Cited
US5055802A
Cited
US5070310A
Cited
US5448755A
Cited
EP0579978A1
Cited
US5331293A
Cited
US5416435A
Cited
US5701602A
Cited
WO1995010141A1
Cited
US5493700A
Cited
US5511235A
Cited
US5548250A
Cited
EP0726508A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |