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US5943252A
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Content addressable memory
Assignee: FOOTHILLS IP LLC
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Filing: 1997-09-04
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Granted: 1999-08-24
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Expires: 2017-09-04
Abstract
Abstract A content addressable memory employs a word-sliced architecture, in order to localize word match logic, and a global data bus, to convey data between the memory input/output circuitry and the plurality of word slices. Timing information is embedded in the global data bus in the form of a model global data signal. This signal interacts with two major control signals to self-time the memory. The number of major control signals is such that all possible memory states are uniquely represented, but the memory cannot power-up in an invalid or unrecoverable state. Three model timing paths are used to match the delay of the self-timing loop with that of the actual operation: one each for READ, WRITE and SEARCH.
Inventors
- 👤 Kenneth James Schultz
- 👤 Farhad Shafai
- 👤 Garnet Frederick Randall Gibson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:50
CPC Classifications
G; G11; G11C; G11C15/00; G11C15/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
103 words
A content addressable memory (CAM) in which all bits of a given word are in physically adjacent columns of word-slice structure and all columns associated with a given bit are distributed, the group of adjacent columns being associated with a word, multiple words occupying multiple rows thereof, the CAM comprising: a global data bus for conveying data between the word slices and data input/output circuitry; and a model global data line for conveying a model global data signal having transitions corresponding to transitions of the data conveyed by the global data bus, so as to model the delay of the global data bus.
Claim 2
Dependent Claim
103 words
A content addressable memory (CAM) in which all bits of a given word are in physically adjacent columns of word-slice structure and all columns associated with a given bit are distributed, the group of adjacent columns being associated with a word, multiple words occupying multiple rows thereof, the CAM comprising: a global data bus for conveying data between the word slices and data input/output circuitry; and a model global data line for conveying a model global data signal having transitions corresponding to transitions of the data conveyed by the global data bus, so as to model the delay of the global data bus.
Claim 3
Dependent Claim
26 words
The CAM of claim 1, further comprising control means responsive to first and second control signals for selecting read, write and search operations of the CAM.
Claim 4
Dependent Claim
85 words
The CAM of claim 2, wherein the control means comprises means for making the model global data signal have transitions in response to the first and second control signals, the initial transition of the model global data signal initiating a transition of a given cycle initiated by an initial transition of at least one of the first and second control signals, the second transition of the model global data signal initiating the second transition of at least one of the first and second control signals.
Claim 5
Dependent Claim
65 words
The CAM of claim 3, wherein the control means further comprises: means for driving data from the input/output circuitry to the word slices in either the write operation or the search operation in response to one of the first and second control signals; and means for decoding the data in either the write operation or the read operation in response to the other control signal.
Claim 6
Dependent Claim
47 words
The CAM of claim 3, wherein the selection of the operations is made externally by third, fourth and fifth control signals which are independent and mutually exclusive from each other, the first and second control signals being a combination of the third, fourth and fifth control signals.
Claim 7
Dependent Claim
29 words
The CAM of claim 5, wherein the control means further comprises means for propagating the data from one word slice to another in response to a sixth control signal.
Claim 8
Dependent Claim
84 words
The CAM of claim 1, further comprising a self-timing loop associated with a read operation for making use of a path from memory control circuitry to the selected word slice including sense amplifiers connected to bit lines of the word slice, the sense amplifiers being activated in the read operation, the outputs of the sense amplifiers being logically combined, so as to gate the model global data signal to perform its transition independently of the transition of the data sensed by the sense amplifiers.
Claim 9
Dependent Claim
41 words
The CAM of claim 1, further comprising a self-timing loop associated with a write operation employing a model word line, the signal of which causes the model global data signal to perform its transition after the completion of the write operation.
Claim 10
Dependent Claim
63 words
The CAM of claim 1, further comprising a self-timing loop associated with a search operation for making use of (a) a model word which is hard-wired to always match or always mismatch, in either case and (b) a path through means for encoding a search result from the model word to means for causing the model global data signal to perform its transition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |