Patent US5942910A successfully refreshed from Google Patents.
US5942910A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuit for providing accurate voltage sensing for a power transistor, or the like
Assignee: Texas Instruments Inc
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Filing: 1997-08-28
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Granted: 1999-08-24
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Expires: 2017-08-28
Abstract
Abstract A circuit (10) is disclosed for enabling voltage to be sensed across a power transistor (12) of the type which has first and second active regions, such as source (85) and drain (76) regions of an MOS transistor (12), or emitter and collector regions of a bipolar transistor (42), in a semiconductor substrate (72), with the first region (76) located along a first lateral extent in the substrate (72) to have ends at terminal locations (D1,S1) of the first lateral extent and the second region located along a second lateral extent in the substrate (72) to have ends at terminal locations (D2,S2) of the second lateral extent. The circuit (10) includes a first conductive line (20) connected to the first region at said terminal locations (D1,D2) of the first lateral extent, and a first voltage sensing connection (22) to a midpoint of the first conductive line (20). A second conductive line (28) is connected to the second region at the terminal locations (S1,S2) of the second lateral extent, and a second voltage sensing connection is made to a midpoint (34) of the second conductive line (28). The conductive lines (20,28) may be, for example, metal, polysilicon, or other suitable material.
Inventors
- 👤 Baoson Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:29
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/2607; G01R31/2621
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
139 words
A circuit for enabling voltage to be sensed across a power transistor having first and second active regions in a semiconductor substrate, said first active region being located along a first lateral extent in said substrate to have ends at terminal locations of said first lateral extent and said second active region being located along a second lateral extent in said substrate to have drain ends at terminal locations of said second lateral extent, comprising: a first conductive line connected to said first active region at said terminal locations of said first lateral extent; a first voltage sensing connection at a midpoint of said first conductive line; a second conductive line connected to said second active region at said terminal locations of said second lateral extent; a second voltage sensing connection at a midpoint of said second conductive line.
Claim 2
Dependent Claim
139 words
A circuit for enabling voltage to be sensed across a power transistor having first and second active regions in a semiconductor substrate, said first active region being located along a first lateral extent in said substrate to have ends at terminal locations of said first lateral extent and said second active region being located along a second lateral extent in said substrate to have drain ends at terminal locations of said second lateral extent, comprising: a first conductive line connected to said first active region at said terminal locations of said first lateral extent; a first voltage sensing connection at a midpoint of said first conductive line; a second conductive line connected to said second active region at said terminal locations of said second lateral extent; a second voltage sensing connection at a midpoint of said second conductive line.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein said first and second conductive lines are metal lines.
Claim 4
Dependent Claim
20 words
The circuit of claim 2 wherein said first and second conductive lines are located on a surface of said substrate.
Claim 5
Dependent Claim
21 words
The circuit of claim 1 wherein said first and second conductive lines extend adjacent said respective first and second active regions.
Claim 6
Dependent Claim
22 words
The circuit of claim 1 wherein said first and second active regions are respectively source and drain regions of an MOS transistor.
Claim 7
Dependent Claim
22 words
The circuit of claim 1 wherein said first and second active regions are respectively emitter and collector regions of a bipolar transistor.
Claim 8
Dependent Claim
127 words
A circuit for sensing a voltage across a power transistor having a first and second active regions in a semiconductor substrate, said first active region being located along a first lateral extent in said substrate to have ends at terminal locations of said first lateral extent and said second active region being located along a second lateral extent in said substrate to have drain ends at terminal locations of said second lateral extent, comprising: a first conductive line connected to said first active region at said terminal locations of said first lateral extent; a second conductive line connected to said second active region at said terminal locations of said second lateral extent; a voltage sensing circuit connected between respective midpoints of said first and second conductive lines.
Claim 9
Dependent Claim
127 words
A circuit for sensing a voltage across a power transistor having a first and second active regions in a semiconductor substrate, said first active region being located along a first lateral extent in said substrate to have ends at terminal locations of said first lateral extent and said second active region being located along a second lateral extent in said substrate to have drain ends at terminal locations of said second lateral extent, comprising: a first conductive line connected to said first active region at said terminal locations of said first lateral extent; a second conductive line connected to said second active region at said terminal locations of said second lateral extent; a voltage sensing circuit connected between respective midpoints of said first and second conductive lines.
Claim 10
Dependent Claim
15 words
The circuit of claim 5 wherein said first and second conductive lines are metal lines.
Claim 11
Dependent Claim
20 words
The circuit of claim 6 wherein said first and second conductive lines are located on a surface of said substrate.
Claim 12
Dependent Claim
21 words
The circuit of claim 5 wherein said first and second conductive lines extend adjacent said respective first and second active regions.
Claim 13
Dependent Claim
22 words
The circuit of claim 5 wherein said first and second active regions are respectively source and drain regions of an MOS transistor.
Claim 14
Dependent Claim
22 words
The circuit of claim 5 wherein said first and second active regions are respectively emitter and collector regions of a bipolar transistor.
Claim 15
Independent Claim
130 words
A method for sensing voltage across a power transistor having first and second active regions in a semiconductor substrate, said first active region being located along a first lateral extent in said substrate to have ends at terminal locations of said first lateral extent and said second active region being located along a second lateral extent in said substrate to have ends at terminal locations of said second lateral extent, comprising: providing a first conductive line connected to said first active region at said terminal locations of said first lateral extent; providing a second conductive line connected to said second active region at said terminal locations of said second lateral extent; sensing a voltage between a midpoint of said first conductive line and a midpoint of said second conductive line.
Claim 16
Independent Claim
130 words
A method for sensing voltage across a power transistor having first and second active regions in a semiconductor substrate, said first active region being located along a first lateral extent in said substrate to have ends at terminal locations of said first lateral extent and said second active region being located along a second lateral extent in said substrate to have ends at terminal locations of said second lateral extent, comprising: providing a first conductive line connected to said first active region at said terminal locations of said first lateral extent; providing a second conductive line connected to said second active region at said terminal locations of said second lateral extent; sensing a voltage between a midpoint of said first conductive line and a midpoint of said second conductive line.
Claim 17
Dependent Claim
21 words
The method of claim 9 wherein said steps of providing first and second conductive lines comprises providing first and metal lines.
Claim 18
Dependent Claim
29 words
The method of claim 10 wherein said steps of providing first and second conductive lines comprises locating said first and second conductive lines on a surface of said substrate.
Claim 19
Dependent Claim
35 words
The method of claim 9 wherein said step of providing first and second conductive lines comprises establishing said first and second conductive lines at locations adjacent respective ones of said first and second active regions.
Claim 20
Dependent Claim
82 words
The method of claim 9 wherein said step of providing a first conductive line connected to said first active region at said terminal locations of said first lateral extent comprises connecting a conductive line to a source region of an MOS power transistor, and wherein said step of providing a second conductive line connected to said second active region at said terminal locations of said second lateral extent comprises connecting a conductive line to a drain region of said MOS power transistor.
Claim 21
Dependent Claim
83 words
The method of claim 9 wherein said step of providing a first conductive line connected to said first active region at said terminal locations of said first lateral extent comprises connecting a conductive line to an emitter region of a bipolar power transistor, and wherein said step of providing a second conductive line connected to said second active region at said terminal locations of said second lateral extent comprises connecting a conductive line connected to a collector region of said bipolar power transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-23 | 2003-02-22 | 2003-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-23 | 2007-02-22 | 2007-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-23 | 2011-02-22 | 2011-08-24 | $7700.00 | Window Closed / Lapsed |