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US5939745A Expired / Lapsed US ⏱️ 0.0 years remaining

Dynamic access memory using silicon-on-insulator

Assignee: Samsung Electronics Co Ltd
•
Filing: 1997-04-15
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Granted: 1999-08-17
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Expires: 2017-04-15
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Abstract

Abstract The present invention discloses a method for making a dynamic random access memory by silicon-on-insulator comprising the steps of: dividing a cell area and a peripheral area on a first silicon substrate and recessing just the cell area where a memory device is formed; forming a first insulating layer by isolation of electrical elements in order to divide an active region and a passive region; forming and patterning a first conductive layer through a contact to which the active region and a capacitor are connected on the insulating layer to form a storage node; forming a dielectric layer of the capacitor on the storage node; forming and patterning a polysilicon layer on the dielectric layer to form a storage node; forming a second insulating layer on the plate node and planarizing the insulating layer by thermal treatment; forming a third conductive layer to a predetermined thickness on the planarized insulating layer; polishing and planarizing the third conductive layer by chemical-mechanical polishing technique, using the second insulating layer as an etchstopper and bonding a second silicon substrate on the planarized third conductive layer; planarizing a backside of the first substrate by a chemical-mechanical polishing technique and exposing the active region; and forming a switching element on the forming a bit line.

Inventors

  • 👤 Kyucharn Park
  • 👤 Yeseung Lee
  • 👤 Cheonsu Ban
  • 👤 Kyungwook Lee

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 08:45
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/33; H10B12/01; H10B12/02; H10B12/03; H10B12/036

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 139 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having top, bottom, and side surfaces, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having top and bottom surfaces, wherein the bottom surface of the silicon-on-insulator is higher than the bottom surface of the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 2
Dependent Claim 139 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having top, bottom, and side surfaces, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having top and bottom surfaces, wherein the bottom surface of the silicon-on-insulator is higher than the bottom surface of the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 3
Dependent Claim 16 words
The semiconductor memory of claim 1, further comprising: a gate electrode formed over the silicon-on-insulator layer.
Claim 4
Dependent Claim 36 words
The semiconductor memory of claim 1, wherein the storage node comprises a first doped polysilicon layer in electrical contact with the silicon-on-insulator layer and a second doped polysilicon layer formed under the first doped polysilicon layer.
Claim 5
Dependent Claim 23 words
The semiconductor memory of claim 3, wherein the impurity of the first doped polysilicon layer is diffused from the second doped polysilicon layer.
Claim 6
Dependent Claim 23 words
The semiconductor memory of claim 1, wherein the plate node extends to a border between the memory cell portion and the peripheral portion.
Claim 7
Dependent Claim 15 words
The semiconductor memory of claim 1, wherein the silicon-on-insulator layer is thinner than the substrate.
Claim 8
Dependent Claim 22 words
The semiconductor memory of claim 1, wherein the bottom surface of the silicon-on-insulator is higher than the top surface of the substrate.
Claim 9
Dependent Claim 123 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having a thickness thinner than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 10
Dependent Claim 123 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having a thickness thinner than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 11
Dependent Claim 124 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, located at a higher level than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 12
Dependent Claim 124 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, located at a higher level than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.

References Cited (Backward Citations)

US4907047A Cited
JPH0260163A Cited
US5102819A Cited
US5119155A Cited
JPH04107858A Cited
US5414285A Cited
US5414655A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-08-16 2003-02-15 2003-08-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-08-16 2007-02-15 2007-08-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-08-16 2011-02-15 2011-08-17 $7700.00 Window Closed / Lapsed

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