Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
139 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having top, bottom, and side surfaces, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having top and bottom surfaces, wherein the bottom surface of the silicon-on-insulator is higher than the bottom surface of the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 2
Dependent Claim
139 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having top, bottom, and side surfaces, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having top and bottom surfaces, wherein the bottom surface of the silicon-on-insulator is higher than the bottom surface of the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 3
Dependent Claim
16 words
The semiconductor memory of claim 1, further comprising: a gate electrode formed over the silicon-on-insulator layer.
Claim 4
Dependent Claim
36 words
The semiconductor memory of claim 1, wherein the storage node comprises a first doped polysilicon layer in electrical contact with the silicon-on-insulator layer and a second doped polysilicon layer formed under the first doped polysilicon layer.
Claim 5
Dependent Claim
23 words
The semiconductor memory of claim 3, wherein the impurity of the first doped polysilicon layer is diffused from the second doped polysilicon layer.
Claim 6
Dependent Claim
23 words
The semiconductor memory of claim 1, wherein the plate node extends to a border between the memory cell portion and the peripheral portion.
Claim 7
Dependent Claim
15 words
The semiconductor memory of claim 1, wherein the silicon-on-insulator layer is thinner than the substrate.
Claim 8
Dependent Claim
22 words
The semiconductor memory of claim 1, wherein the bottom surface of the silicon-on-insulator is higher than the top surface of the substrate.
Claim 9
Dependent Claim
123 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having a thickness thinner than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 10
Dependent Claim
123 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, having a thickness thinner than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 11
Dependent Claim
124 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, located at a higher level than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.
Claim 12
Dependent Claim
124 words
A semiconductor memory having a memory cell portion and a peripheral portion, comprising: a substrate having a side surface, the substrate being formed only in the peripheral portion; a silicon-on-insulator layer, formed in the memory cell portion, located at a higher level than the substrate; a first insulating layer formed under the silicon-on-insulator layer and on the side surface of the substrate, wherein a contact hole is formed in a portion of the first insulating layer in the memory cell portion to expose the silicon-on-insulator; and a capacitor formed in the memory cell area, wherein the capacitor has a storage node electrically connected to the silicon-on-insulator layer through the contact hole, an insulator surrounding the storage node, and a plate node surrounding the insulator.