MIS semiconductor device and method for fabricating the same

Claim 2

A semiconductor device comprising: a substrate having an insulating surface; an active matrix circuit formed on the insulating surface; at least one driver, formed on the insulating surface, for driving the active matrix circuit; and a circuit connected with said at least one driver provided on the insulating surface, said circuit comprising at least one of a memory, a CPU, an input port, and a correcting memory, wherein at least one of said active matrix circuit, said driver, and said circuit comprises at least one P-channel thin film transistor and at least one N-channel thin film transistor, each of said P-channel and N-channel thin film transistors comprising: a semiconductor film formed over the substrate; a first region including a channel region formed within said semiconductor film; a pair of second regions formed within said semiconductor film and doped with an impurity for giving a one conductivity type thereto, said second regions functioning as source and drain regions; a pair of third regions, each being interposed between said first region and said second regions, respectively; and a gate electrode located adjacent to said first region with a gate insulating film interposed therebetween, wherein widths of said third regions in said N-channel thin film transistors are larger than those in said P-channel thin film transistors.

Claim 3

A device according to claim 1 wherein said gate electrode is provided over said semiconductor film.

Claim 4

A device according to claim 1 wherein one boundary of one of said third regions is coincident with an edge of said gate electrode.

Claim 5

A device according to claim 1 wherein said third regions comprise LDD regions and/or offset regions.

Claim 6

A device according to claim 1 wherein said third regions include at least two regions having different resistivities.

Claim 7

A device according to claim 1 wherein said substrate is selected from the group consisting of a glass substrate, a monocrystal semiconductor substrate, a non-alkaline glass substrate, and a silica substrate.

Claim 8

A device according to claim 1 wherein a material of said semiconductor film is selected from the group consisting of silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide, and silicon.

Claim 9

A device according to claim 1 wherein a material of said gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten, and molybdenum.

Claim 10

A semiconductor device comprising: a substrate having an insulating surface; an active matrix circuit formed on the insulting surface; at least one driver, formed on the insulating surface, for driving the active matrix circuit; and a circuit connected with said at least one driver provided on the insulating surface, said circuit comprising at least one of a memory, a CPU, an input port, and a correcting memory, wherein at least one of said active matrix circuit, said driver, and said circuit comprises at least one P-channel thin film transistor and at least one N-channel thin film transistor, each of said N-channel and P-channel thin film transistors comprising: a semiconductor film formed over the substrate; a first region including a channel region formed within said semiconductor film; a pair of second regions formed within said semiconductor film and doped with an impurity for giving a one conductivity type thereto; a pair of third regions, each being interposed between said first region and said second regions, respectively; and a gate electrode located adjacent to said first region with a gate insulating film interposed therebetween, wherein channel length in said N-channel thin film transistor is larger than that in said P-channel thin film transistor, and wherein widths of said third regions in said N-channel thin film transistors are greater than widths of said third regions in said P-channel thin film transistors.

Claim 11

A semiconductor device comprising: a substrate having an insulating surface; an active matrix circuit formed on the insulting surface; at least one driver, formed on the insulating surface, for driving the active matrix circuit; and a circuit connected with said at least one driver provided on the insulating surface, said circuit comprising at least one of a memory, a CPU, an input port, and a correcting memory, wherein at least one of said active matrix circuit, said driver, and said circuit comprises at least one P-channel thin film transistor and at least one N-channel thin film transistor, each of said N-channel and P-channel thin film transistors comprising: a semiconductor film formed over the substrate; a first region including a channel region formed within said semiconductor film; a pair of second regions formed within said semiconductor film and doped with an impurity for giving a one conductivity type thereto; a pair of third regions, each being interposed between said first region and said second regions, respectively; and a gate electrode located adjacent to said first region with a gate insulating film interposed therebetween, wherein channel length in said N-channel thin film transistor is larger than that in said P-channel thin film transistor, and wherein widths of said third regions in said N-channel thin film transistors are greater than widths of said third regions in said P-channel thin film transistors.

Claim 12

A device according to claim 9 wherein said gate electrode is provided over said semiconductor film.

Claim 13

A device according to claim 9 wherein said substrate is selected from the group consisting of a glass substrate, a monocrystal semiconductor substrate, a non-alkaline glass substrate, and a silica substrate.

Claim 14

A device according to claim 9 wherein a material of said semiconductor film is selected from the group consisting of silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide, and silicon.

Claim 15

A device according to claim 9 wherein a material of said gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten, and molybdenum.

Claim 16

A semiconductor device comprising: a substrate having an insulating surface; an active matrix circuit formed on the insulating surface; at least one driver, formed on the insulating surface, for driving the active matrix circuit; and a circuit connected with said at least one driver provided on the insulating surface, said circuit comprising at least one of a memory, a CPU, an input port, and a correcting memory, wherein at least one of said active matrix circuit, said driver, and said circuit comprises at least one P-channel thin film transistor and at least one N-channel thin film transistor, each of said N-channel and P-channel thin film transistors comprising: a semiconductor film formed over the substrate; a first region including a channel region formed within said semiconductor film; a pair of second regions formed within said semiconductor film and doped with an impurity for giving a one conductivity type thereto; a pair of third regions, each being interposed between said first region and said second regions, respectively, each third region comprising a LDD region doped with said impurity at a concentration smaller than that in said second regions; and a gate electrode located adjacent to said first region with a gate insulating film interposed therebetween, edges of said gate electrode being aligned with those of the first regions, wherein width of said LDD regions of said N-channel thin film transistor is larger than that of said P-channel thin film transistor.

Claim 17

A semiconductor device comprising: a substrate having an insulating surface; an active matrix circuit formed on the insulating surface; at least one driver, formed on the insulating surface, for driving the active matrix circuit; and a circuit connected with said at least one driver provided on the insulating surface, said circuit comprising at least one of a memory, a CPU, an input port, and a correcting memory, wherein at least one of said active matrix circuit, said driver, and said circuit comprises at least one P-channel thin film transistor and at least one N-channel thin film transistor, each of said N-channel and P-channel thin film transistors comprising: a semiconductor film formed over the substrate; a first region including a channel region formed within said semiconductor film; a pair of second regions formed within said semiconductor film and doped with an impurity for giving a one conductivity type thereto; a pair of third regions, each being interposed between said first region and said second regions, respectively, each third region comprising a LDD region doped with said impurity at a concentration smaller than that in said second regions; and a gate electrode located adjacent to said first region with a gate insulating film interposed therebetween, edges of said gate electrode being aligned with those of the first regions, wherein width of said LDD regions of said N-channel thin film transistor is larger than that of said P-channel thin film transistor.

Claim 18

A device according to claim 14 wherein said gate electrode is provided over said semiconductor film.

Claim 19

A device according to claim 14 wherein said substrate is selected from the group consisting of a glass substrate, a monocrystal semiconductor substrate, a non-alkaline glass substrate, and a silica substrate.

Claim 20

A device according to claim 14 wherein a material of said semiconductor film is selected from the group consisting of silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide, and silicon.

Claim 21

A device according to claim 14 wherein a material of said gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten, and molybdenum.

Claim 22

A semiconductor device comprising: a substrate having an insulating surface; an active matrix circuit formed on the insulating surface; at least one driver, formed on the insulating surface, for driving the active matrix circuit; and a circuit connected with said at least one driver provided on the insulating surface, said circuit comprising at least one of a memory, a CPU, an input port, and a correcting memory, wherein at least one of said active matrix circuit, said driver, and said circuit comprises at least one P-channel thin film transistor and at least one N-channel thin film transistor, each of said N-channel and P-channel thin film transistors comprising: a semiconductor film formed over the substrate; a first region including a channel region formed within said semiconductor film; a pair of second regions formed within said semiconductor film and doped with an impurity for giving a one conductivity type thereto; a pair of third regions, each being interposed between said first region and said second regions, respectively, each third region comprising a LDD region doped with said impurity at a concentration smaller than that in said second regions; and a gate electrode located adjacent to said first region with a gate insulating film interposed therebetween, wherein widths of said LDD regions in said P-channel thin film transistors are 0-0.2 μm, and wherein widths of said LDD regions in said N-channel thin film transistors are greater than said widths of said LDD regions in said P-channel transistors.

Claim 23

A semiconductor device comprising: a substrate having an insulating surface; an active matrix circuit formed on the insulating surface; at least one driver, formed on the insulating surface, for driving the active matrix circuit; and a circuit connected with said at least one driver provided on the insulating surface, said circuit comprising at least one of a memory, a CPU, an input port, and a correcting memory, wherein at least one of said active matrix circuit, said driver, and said circuit comprises at least one P-channel thin film transistor and at least one N-channel thin film transistor, each of said N-channel and P-channel thin film transistors comprising: a semiconductor film formed over the substrate; a first region including a channel region formed within said semiconductor film; a pair of second regions formed within said semiconductor film and doped with an impurity for giving a one conductivity type thereto; a pair of third regions, each being interposed between said first region and said second regions, respectively, each third region comprising a LDD region doped with said impurity at a concentration smaller than that in said second regions; and a gate electrode located adjacent to said first region with a gate insulating film interposed therebetween, wherein widths of said LDD regions in said P-channel thin film transistors are 0-0.2 μm, and wherein widths of said LDD regions in said N-channel thin film transistors are greater than said widths of said LDD regions in said P-channel transistors.

Claim 24

A device according to claim 19 wherein said gate electrode is provided over said semiconductor film.

Claim 25

A device according to claim 19 wherein said substrate is selected from the group consisting of a glass substrate, a monocrystal semiconductor substrate, a non-alkaline glass substrate, and a silica substrate.

Claim 26

A device according to claim 19 wherein a material of said semiconductor film is selected from the group consisting of silicon-germanium alloy, silicon carbide, germanium, cadmium selenite, cadmium sulfide, gallium arsenide, and silicon.

Claim 27

A device according to claim 19 wherein a material of said gate electrode is selected from the group consisting of aluminum, tantalum, titanium, silicon, tantalum nitride, titanium nitride, tungsten, and molybdenum.