US5937170A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data communications with processor-assertable addresses mapped to peripheral-accessible-addresses-times-command product space
Assignee: Hanger Solutions LLC
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Filing: 1997-02-21
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Granted: 1999-08-10
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Expires: 2017-02-21
Abstract
Abstract A computer system includes a microprocessor running in big-endian mode and both big-endian and little-endian peripherals, including a little-endian SCSI controller that controls a hard disk. When a program calls for a data transfer between the hard disk and random-access memory, the operating system determines a peripheral-accessible memory address range for the data transfer. A bridge driver intercepts this range and determines whether or not the data needs to be swizzled to take into account differing endianness. The determination is encoded into the most significant bit of a processor-assertable address range, and the bits of lesser significance indicate the peripheral-accessible address range. The processor-assertable address range is conveyed to the SCSI controller originating the data transfer. A communications bridge extracts the processor-assertable address from the origination information from the SCSI controller. The bridge maps the processor-assertable address range to a product space of peripheral-accessible addresses and a command set. The mapping indicates the peripheral-accessible address range intended by the operating system and an indication that swizzling need to be performed. In addition, the second most significant bit of the processor-assertable address is used to indicate that cache snooping is required for the transfer. The invention efficiently allows peripherals designed for one endian environment to work in a different endian environment.
Inventors
- 👤 Alessandro Bedarida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:14
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4009; G06F13/4013
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
217 words
A data communications bridge for managing communication between a microprocessor, an addressable assembly, and plural peripherals, said microprocessor defining a processor-assertable address space of processor-assertable addresses, said addressable assembly defining a populated address space of populated addresses including a peripheral-accessible address space of peripheral-accessible addresses, said peripherals initiating communications with said addressable assembly in part by transmitting indications of processor-assertable address ranges, said bridge comprising: interface means for receiving data from and transmitting data to said microprocessor, said addressable assembly, and said peripherals, and for receiving address indications from said peripherals; address detection means for detecting a processor-assertable address range indication transmitted by one of said peripherals; mapping means for selecting a peripheral-accessible address range and a data operation as a function of said processor-assertable address range, said peripheral-accessible address range being selected from said peripheral accessible addresses, said data operation being selected from a set of plural data operations, said mapping means being coupled to said address detection means for receiving said address range indication, said mapping means being coupled to said interface means and said address detection means, said mapping means causing said peripheral-accessible address range to be accessed; and operator means for performing or causing to be performed on a data transfer said data operation, said operator means being coupled to said mapping means.
Claim 2
Dependent Claim
217 words
A data communications bridge for managing communication between a microprocessor, an addressable assembly, and plural peripherals, said microprocessor defining a processor-assertable address space of processor-assertable addresses, said addressable assembly defining a populated address space of populated addresses including a peripheral-accessible address space of peripheral-accessible addresses, said peripherals initiating communications with said addressable assembly in part by transmitting indications of processor-assertable address ranges, said bridge comprising: interface means for receiving data from and transmitting data to said microprocessor, said addressable assembly, and said peripherals, and for receiving address indications from said peripherals; address detection means for detecting a processor-assertable address range indication transmitted by one of said peripherals; mapping means for selecting a peripheral-accessible address range and a data operation as a function of said processor-assertable address range, said peripheral-accessible address range being selected from said peripheral accessible addresses, said data operation being selected from a set of plural data operations, said mapping means being coupled to said address detection means for receiving said address range indication, said mapping means being coupled to said interface means and said address detection means, said mapping means causing said peripheral-accessible address range to be accessed; and operator means for performing or causing to be performed on a data transfer said data operation, said operator means being coupled to said mapping means.
Claim 3
Dependent Claim
33 words
A data communications bridge as recited in claim 1 wherein the mapping effected by said mapping means is programmable accordingly to programming codes transmitted by said microprocessor and received by said interface means.
Claim 4
Dependent Claim
20 words
A data communications bridge as recited in claim 1 wherein said data operations collectively provide for swizzling and not swizzling.
Claim 5
Dependent Claim
22 words
A data communications bridge as recited in claim 1 wherein said data operations collectively provide for cache snooping and not cache snooping.
Claim 6
Independent Claim
106 words
A method of managing communication between a peripheral and an addressable assembly, said method comprising the steps of: a) having a microprocessor direct said peripheral to originate a data transfer with said addressable assembly at a specified processor-assertable address range; b) having a communications bridge select a peripheral-accessible address range and a data operation as a function of said processor-assertable address range, said peripheral-accessible address range being selected from a populated address range of said addressable assembly, said data operation being selected from a set of plural data operations; and c) completing said data transfer by accessing said peripheral-accessible address range and executing said data operation.
Claim 7
Independent Claim
106 words
A method of managing communication between a peripheral and an addressable assembly, said method comprising the steps of: a) having a microprocessor direct said peripheral to originate a data transfer with said addressable assembly at a specified processor-assertable address range; b) having a communications bridge select a peripheral-accessible address range and a data operation as a function of said processor-assertable address range, said peripheral-accessible address range being selected from a populated address range of said addressable assembly, said data operation being selected from a set of plural data operations; and c) completing said data transfer by accessing said peripheral-accessible address range and executing said data operation.
Claim 8
Dependent Claim
26 words
A method as recited in claim 5 further comprising a step of, before step a), having said microprocessor program said communications bridge to determine said function.
Claim 9
Dependent Claim
19 words
A method as recited in claim 5 wherein said set of data operations collectively include swizzling and not swizzling.
Claim 10
Dependent Claim
21 words
A method as recited in claim 5 wherein said set of data operations collectively include cache snooping and not cache snooping.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-09 | 2003-02-08 | 2003-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-09 | 2007-02-08 | 2007-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-09 | 2011-02-08 | 2011-08-10 | $7700.00 | Window Closed / Lapsed |