Integrated circuits having metallic fuse links

Claim 2

An integrated circuit comprising: a semiconductor substrate; an insulating layer on said semiconductor substrate; a first metal wiring layer having an end surface and an upper surface on said insulating layer; a second metal wiring layer having an end surface and an upper surface on said insulating layer, wherein said first and said second metal wiring layers are arranged so that the end surface of said first metal wiring layer opposes the end surface of said second metal wiring layer; a metallic fuse link on the upper surface and the end surface of said first metal wiring layer and on the upper surface and the end surface of said second metal wiring layer, and on a surface of said insulating layer located between said first and second metal wiring layers; an interlevel insulating layer directly on and in contact with said insulating layer, said interlevel insulating layer having a groove therein which exposes said metallic fuse link and a portion of said insulating layer extending adjacent said metallic fuse link; and a blanket protection layer on said metallic fuse link.

Claim 3

The integrated circuit of claim 1, wherein said metallic fuse link comprises TiN or TiW.

Claim 4

The integrated circuit of claim 2, wherein said first and second metal wiring layers comprise a layer of pure aluminum or aluminum alloy.

Claim 5

The integrated circuit of claim 2, wherein said first and second metal wiring layers comprise a barrier metal layer, and an aluminum or aluminum alloy layer on the barrier metal layer.

Claim 6

The integrated circuit of claim 2, wherein said groove has an area larger than an area covered by a laser beam used to sever said metallic fuse link.

Claim 7

The integrated circuit of claim 4, wherein said barrier metal layer comprises a TiN layer.

Claim 8

An integrated circuit comprising: an integrated circuit on a semiconductor substrate; an insulating layer on said integrated circuit; a plurality of metal wiring layers on said insulating layer that connect to said integrated circuit, said plurality of metal wiring layers having end surfaces and upper surfaces, wherein a first and a second metal wiring layer in the plurality thereof are located so that the end surface of said first metal wiring layer opposes the end surface of said second metal wiring layer; a metallic fuse link on the upper surface and the end surface of said first metal wiring layer and on the upper surface and the end surface of said second metal wiring layer, and on a surface of said insulating layer located between the opposing end surfaces of said first and second metal wiring layers; and an interlevel insulating layer directly on and in contact with said insulating layer and said metallic fuse link, said interlevel insulating layer having a groove therein which exposes the metallic fuse link and a portion of said interlevel insulating layer extending adjacent said metallic fuse link.

Claim 9

An integrated circuit comprising: an integrated circuit on a semiconductor substrate; an insulating layer on said integrated circuit; a plurality of metal wiring layers on said insulating layer that connect to said integrated circuit, said plurality of metal wiring layers having end surfaces and upper surfaces, wherein a first and a second metal wiring layer in the plurality thereof are located so that the end surface of said first metal wiring layer opposes the end surface of said second metal wiring layer; a metallic fuse link on the upper surface and the end surface of said first metal wiring layer and on the upper surface and the end surface of said second metal wiring layer, and on a surface of said insulating layer located between the opposing end surfaces of said first and second metal wiring layers; and an interlevel insulating layer directly on and in contact with said insulating layer and said metallic fuse link, said interlevel insulating layer having a groove therein which exposes the metallic fuse link and a portion of said interlevel insulating layer extending adjacent said metallic fuse link.

Claim 10

The integrated circuit of claim 7, wherein said metallic fuse link comprises a TiN or TiW layer.

Claim 11

The integrated circuit of claim 8, wherein said first metal wiring layer and said second metal wiring layer comprise a barrier metal layer and a metal interconnection layer on said barrier metal layer.

Claim 12

The integrated circuit of claim 9, wherein said barrier metal layer comprises a TiN layer and said metal interconnection layer comprises an aluminum or aluminum alloy layer.

Claim 13

The integrated circuit of claim 7, wherein said groove has an area larger than an area covered by a laser beam used to sever the metallic fuse link.

Claim 14

The integrated circuit of claim 11, further comprising a plurality of upper metal interconnections, on said interlevel insulating layer, that connect to said metallic fuse link; and a blanket protection layer on said exposed metallic fuse link and said upper metal interconnections.