Apparatus and method for high speed data and command transfer over an interface

Claim 1

A method for data transfer over an interface, the interface including a processor and connected to data terminal equipment, a data communications device coupleable to a communications channel and to the interface for data transfer between the communications channel and the data terminal equipment, the method comprising; (a) receiving a non-markable interrupt signal; (b) when the interrupt signal indicates a write command from the data terminal equipment, transferring data from the interface to a memory for transmission over the communications channel; and (c) when the interrupt signal indicates data received from the communications channel, generating a read command to the data terminal equipment and transferring data from the memory to the data terminal equipment via the interface.

Claim 2

A method for data transfer over an interface, the interface including a processor and connected to data terminal equipment, a data communications device coupleable to a communications channel and to the interface for data transfer between the communications channel and the data terminal equipment, the method comprising; (a) receiving a non-markable interrupt signal; (b) when the interrupt signal indicates a write command from the data terminal equipment, transferring data from the interface to a memory for transmission over the communications channel; and (c) when the interrupt signal indicates data received from the communications channel, generating a read command to the data terminal equipment and transferring data from the memory to the data terminal equipment via the interface.

Claim 15

An apparatus for data transfer across a first interface, the first interface connected to data terminal equipment, the apparatus coupleable to a communications channel and to the first interface for data transfer between the communications channel and the data terminal equipment, the apparatus comprising: a transceiver coupleable to the first interface to transfer data to and from the first interface; a second interface coupleable to the communications channel to receive data from the communications channel and to transmit data over the communications channel; a memory for storage of data; and a processor connected to the transceiver, to the second interface and to the memory, the processor responsive through a set of program instructions to receive a non-maskable interrupt signal and, when the interrupt signal indicates a write command, to transfer data via the transceiver from the first interface to the memory for transmission over the communications channel via the second interface, and when the interrupt signal indicates data received from the communications channel, the processor further responsive to generate a read command and transfer data from the memory to the first interface via the transceiver.

Claim 16

An apparatus for data transfer across a first interface, the first interface connected to data terminal equipment, the apparatus coupleable to a communications channel and to the first interface for data transfer between the communications channel and the data terminal equipment, the apparatus comprising: a transceiver coupleable to the first interface to transfer data to and from the first interface; a second interface coupleable to the communications channel to receive data from the communications channel and to transmit data over the communications channel; a memory for storage of data; and a processor connected to the transceiver, to the second interface and to the memory, the processor responsive through a set of program instructions to receive a non-maskable interrupt signal and, when the interrupt signal indicates a write command, to transfer data via the transceiver from the first interface to the memory for transmission over the communications channel via the second interface, and when the interrupt signal indicates data received from the communications channel, the processor further responsive to generate a read command and transfer data from the memory to the first interface via the transceiver.

Claim 32

An apparatus for data transfer across a first interface, the first interface connected to data terminal equipment, the apparatus coupleable to a communications channel and to the first interface for data transfer between the communications channel and the data terminal equipment, the apparatus comprising: a transceiver coupleable to the first interface to transfer data to and from the first interface; a second interface coupleable to the communications channel to receive data from the communications channel to form received data and to transmit transmissible data over the communications channel; a memory for storage of received data and transmissible data; and a processor connected to the transceiver, to the second interface and to the memory, the processor further having a direct memory access controller, the processor responsive through a set of program instructions to monitor a plurality of interface state parameters and to receive an interrupt signal and, during a secondary interrupt service routine, to configure the direct memory access controller with a first address corresponding to the transceiver in conjunction with the first interface and to configure the direct memory access controller with a second, variable pointer address corresponding to a location in the memory; the processor further responsive, when the interrupt signal indicates a read command of a plurality of commands, via the direct memory access controller, to transfer the received data from the location in the memory corresponding to the second, variable pointer address, to the first address for data transfer over the first interface to the data terminal equipment, and to set a first interface state parameter of the plurality of interface state parameters to indicate a read operation in progress; the processor further responsive, when the interrupt signal indicates a write command of the plurality of commands, via the direct memory access controller, to transfer data from the first address to the memory location corresponding to the second, variable pointer address, to form the transmissible data, and to set a second interface state parameter of the plurality of interface state parameters to indicate a write operation in progress; the processor further responsive, when the interrupt signal indicates a supervisory command of the plurality of commands, to process the supervisory command and transmit an acknowledgement signal to the data terminal equipment via the transceiver and the first interface; and the processor further responsive to determine whether there is a pending command of the plurality of commands prior to returning the first interface to an idle state.

Claim 33

An apparatus for data transfer across a first interface, the first interface connected to data terminal equipment, the apparatus coupleable to a communications channel and to the first interface for data transfer between the communications channel and the data terminal equipment, the apparatus comprising: a transceiver coupleable to the first interface to transfer data to and from the first interface; a second interface coupleable to the communications channel to receive data from the communications channel to form received data and to transmit transmissible data over the communications channel; a memory for storage of received data and transmissible data; and a processor connected to the transceiver, to the second interface and to the memory, the processor further having a direct memory access controller, the processor responsive through a set of program instructions to monitor a plurality of interface state parameters and to receive an interrupt signal and, during a secondary interrupt service routine, to configure the direct memory access controller with a first address corresponding to the transceiver in conjunction with the first interface and to configure the direct memory access controller with a second, variable pointer address corresponding to a location in the memory; the processor further responsive, when the interrupt signal indicates a read command of a plurality of commands, via the direct memory access controller, to transfer the received data from the location in the memory corresponding to the second, variable pointer address, to the first address for data transfer over the first interface to the data terminal equipment, and to set a first interface state parameter of the plurality of interface state parameters to indicate a read operation in progress; the processor further responsive, when the interrupt signal indicates a write command of the plurality of commands, via the direct memory access controller, to transfer data from the first address to the memory location corresponding to the second, variable pointer address, to form the transmissible data, and to set a second interface state parameter of the plurality of interface state parameters to indicate a write operation in progress; the processor further responsive, when the interrupt signal indicates a supervisory command of the plurality of commands, to process the supervisory command and transmit an acknowledgement signal to the data terminal equipment via the transceiver and the first interface; and the processor further responsive to determine whether there is a pending command of the plurality of commands prior to returning the first interface to an idle state.

Claim 34

A method for data transfer over an interface, the interface including a processor and connected to data terminal equipment, a data communications device coupleable to a communications channel and to the interface for data transfer between the communications channel and the data terminal equipment, the method comprising: (a) receiving an interrupt signal; (b) when the interrupt signal indicates a write command from the data terminal equipment, transferring data from the interface to a memory for transmission over the communications channel; and (c) when the interrupt signal indicates data received from the communications channel, generating a read command to the data terminal equipment and transferring data from the memory to the data terminal equipment via the interface (d) monitoring a plurality of interface state parameters wherein the plurality of interface state parameters are periodically monitored to determine whether data has been received from the communications channel for transfer to the data terminal equipment.

Claim 35

A method for data transfer over an interface, the interface including a processor and connected to data terminal equipment, a data communications device coupleable to a communications channel and to the interface for data transfer between the communications channel and the data terminal equipment, the method comprising: (a) receiving an interrupt signal; (b) when the interrupt signal indicates a write command from the data terminal equipment, transferring data from the interface to a memory for transmission over the communications channel; and (c) when the interrupt signal indicates data received from the communications channel, generating a read command to the data terminal equipment and transferring data from the memory to the data terminal equipment via the interface (d) monitoring a plurality of interface state parameters wherein the plurality of interface state parameters are periodically monitored to determine whether data has been received from the communications channel for transfer to the data terminal equipment.

Claim 36

An apparatus for data transfer across a first interface, the first interface connected to data terminal equipment, the apparatus coupleable to a communications channel and to the first interface for data transfer between the communications channel and the data terminal equipment, the apparatus comprising: a transceiver coupleable to the first interface to transfer data to and from the first interface, wherein the transceiver is a parallel transceiver having a multiple bit capacity corresponding to a bit capacity of the first interface; a second interface coupleable to the communications channel to receive data from the communications channel and to transmit data over the communications channel; a memory for storage of data; and a processor connected to the transceiver, to the second interface and to the memory, the processor responsive through a set of program instructions to receive an interrupt signal and, when the interrupt signal indicates a write command, to transfer data via the transceiver from the first interface to the memory for transmission over the communications channel via the second interface, and when the interrupt signal indicates data received from the communications channel, the processor further responsive to generate a read command and transfer data from the memory to the first interface via the transceiver.

Claim 37

An apparatus for data transfer across a first interface, the first interface connected to data terminal equipment, the apparatus coupleable to a communications channel and to the first interface for data transfer between the communications channel and the data terminal equipment, the apparatus comprising: a transceiver coupleable to the first interface to transfer data to and from the first interface, wherein the transceiver is a parallel transceiver having a multiple bit capacity corresponding to a bit capacity of the first interface; a second interface coupleable to the communications channel to receive data from the communications channel and to transmit data over the communications channel; a memory for storage of data; and a processor connected to the transceiver, to the second interface and to the memory, the processor responsive through a set of program instructions to receive an interrupt signal and, when the interrupt signal indicates a write command, to transfer data via the transceiver from the first interface to the memory for transmission over the communications channel via the second interface, and when the interrupt signal indicates data received from the communications channel, the processor further responsive to generate a read command and transfer data from the memory to the first interface via the transceiver.