Variable length code processor and image processor having an integrated coding/decoding circuit

Claim 2

A variable length code processor for encoding data into a variable length code corresponding to its run length and level, and decoding said variable length code into said corresponding run length and level, said variable length code processor comprising: a first memory for storing a variable length coding table for outputting said variable length code using said run length and level as input, a second memory for storing a variable length decoding table for outputting said run length and level using said variable length code as input, and a shifter having a first and second mode, wherein said shifter in the first mode applies a bit shift to said variable length code output by said first memory based on the length of said variable length code, and said shifter in the second mode applies a bit shift to said variable length code to be decoded based on the length of said variable length code decoded on the immediately preceding occasion, and supplies the bit-shifted variable length code to said second memory as input.

Claim 3

A variable length code processor as defined in claim 1, wherein said first and second memory are one and the same.

Claim 4

A variable length code processor as defined in claim 1, wherein said shifter performs a bit shift in N bit units of data, said variable length code processor further comprising: a first variable length code memory for temporarily storing a variable length code of N bits which is currently being decoded, a second variable length code memory for temporarily storing a variable length code of N bits which is to be decoded next, and a selector for selecting a remaining N-i bits in said first variable length code memory and an upper i bits in said N bit variable length code stored in said second memory when the upper i bits in said N bit variable length code stored in said first variable length code memory are decoded, and supplying these to said shifter when said shifter is operating in said second mode.

Claim 5

A variable length code processor as defined in claim 3, wherein: when the decoding of said N bit variable length code stored in said first memory is complete, said N bit variable length code stored in said second memory is transferred to said first variable length code memory, and said variable length code of N bits which is to be decoded next is stored in said second variable length code memory.

Claim 6

A variable length code processor as defined in claim 1, further comprising a K bit adder for cumulative addition of the length of said variable length code, wherein: said shifter performs a 2 K bit unit data bit shift based on a cumulative addition result in said adder.

Claim 7

A variable length code processor as defined in claim 1, wherein said first and second table memories are rewritable.

Claim 8

A variable length code processor for encoding image data into a variable length code, and decoding said variable length code into said image data comprising: a first processing circuit for processing said image data, and outputting run length and level of the image data from the processing result, a variable length code processing circuit for either outputting a variable length code corresponding to said run length and level output by said first processing circuit or outputting said run length and level corresponding to said variable length code, and a second processing circuit for processing said run length and level output by said variable length code processing circuit, and outputting said image data, wherein: said variable length code processing circuit comprises: a first memory for storing a variable length coding table for outputting said variable length code using said run length and level as input, a second memory for storing a variable length decoding table for outputting said run length and level using said variable length code as input, and a shifter having a first and second mode, wherein said shifter in the first mode applies a bit shift to said variable length code output by said first memory based on the length of said variable length code, and said shifter in the second mode applies a bit shift to said variable length code to be decoded based on the length of said variable length code decoded on the immediately preceding occasion, and supplies the bit-shifted variable length code to said second memory as input.

Claim 9

A variable length code processor for encoding image data into a variable length code, and decoding said variable length code into said image data comprising: a first processing circuit for processing said image data, and outputting run length and level of the image data from the processing result, a variable length code processing circuit for either outputting a variable length code corresponding to said run length and level output by said first processing circuit or outputting said run length and level corresponding to said variable length code, and a second processing circuit for processing said run length and level output by said variable length code processing circuit, and outputting said image data, wherein: said variable length code processing circuit comprises: a first memory for storing a variable length coding table for outputting said variable length code using said run length and level as input, a second memory for storing a variable length decoding table for outputting said run length and level using said variable length code as input, and a shifter having a first and second mode, wherein said shifter in the first mode applies a bit shift to said variable length code output by said first memory based on the length of said variable length code, and said shifter in the second mode applies a bit shift to said variable length code to be decoded based on the length of said variable length code decoded on the immediately preceding occasion, and supplies the bit-shifted variable length code to said second memory as input.

Claim 10

A variable length code processor as defined in claim 7, wherein said first and second memory are one and the same.

Claim 11

A variable length code processor as defined in claim 1, wherein said shifter is a barrel shifter.

Claim 12

A variable length code processor as defined in claim 7, wherein said shifter is a barrel shifter.

Claim 13

A variable length code processor as defined in claim 2, further comprising a coding/decoding table selector for downloading either said variable length coding table or said variable length decoding table into said memory.

Claim 14

A variable length code processor as defined in claim 8, further comprising a coding/decoding table selector for downloading either said variable length coding table or said variable length decoding table into said memory.

Claim 15

A variable length code processor as defined in claim 11, wherein said table selector comprises: a microprocessor; a coding table memory for storing said variable length coding table; and a decoding table memory for storing said variable length decoding table, wherein said microprocessor selects either the coding table memory or the decoding table memory for downloading respective tables stored therein into said memory.

Claim 16

A variable length code processor as defined in claim 13, wherein said coding table memory and said decoding table memory are non-volatile memories.

Claim 17

A variable length code processor as defined in claim 8, wherein said table selector comprises: a microprocessor; a coding table memory for storing said variable length coding table; and a decoding table memory for storing said variable length decoding table, wherein said microprocessor selects either the coding table memory or the decoding table memory for downloading respective tables stored therein into said memory.

Claim 18

A variable length code processor as defined in claim 15, wherein said coding table memory and said decoding table memory are non-volatile memories.

Claim 19

A variable length code processor for encoding image data into a variable length code, and decoding said variable length code into said image data comprising: a processing circuit for processing said image data and outputting run length and level of the image data from the processing result; a variable length code processing circuit operable in either a coding mode for outputting a variable length code corresponding to said run length and level output by said first processing circuit or a decoding mode for outputting said run length and level corresponding to said variable length code; and a converting circuit for processing said run length and level output by said variable length code processing circuit, and reconstructing said image data, wherein said variable length code processing circuit comprises: a table memory for storing either a variable length coding table for outputting said variable length code using said run length and level as input in said coding mode of operation, or a variable length decoding table for outputting said run length and level using said variable length code as input in said decoding mode of operation, a shifter which applies either a bit shift to said variable length code output by said table memory based on the length of said variable length code in said coding mode of operation, or a bit shift to said variable length code to be decoded based on the length of said variable length code decoded on the immediately preceding occasion, and supplies the bit-shifted variable length code to said table memory as input in said decoding mode of operation, and a mode selector for selecting whether said variable length code processor operates in said coding mode of operation or said decoding mode of operation and providing either said variable length coding table or said variable length decoding table to said table memory based on the selected mode of operation.

Claim 20

A variable length code processor for encoding image data into a variable length code, and decoding said variable length code into said image data comprising: a processing circuit for processing said image data and outputting run length and level of the image data from the processing result; a variable length code processing circuit operable in either a coding mode for outputting a variable length code corresponding to said run length and level output by said first processing circuit or a decoding mode for outputting said run length and level corresponding to said variable length code; and a converting circuit for processing said run length and level output by said variable length code processing circuit, and reconstructing said image data, wherein said variable length code processing circuit comprises: a table memory for storing either a variable length coding table for outputting said variable length code using said run length and level as input in said coding mode of operation, or a variable length decoding table for outputting said run length and level using said variable length code as input in said decoding mode of operation, a shifter which applies either a bit shift to said variable length code output by said table memory based on the length of said variable length code in said coding mode of operation, or a bit shift to said variable length code to be decoded based on the length of said variable length code decoded on the immediately preceding occasion, and supplies the bit-shifted variable length code to said table memory as input in said decoding mode of operation, and a mode selector for selecting whether said variable length code processor operates in said coding mode of operation or said decoding mode of operation and providing either said variable length coding table or said variable length decoding table to said table memory based on the selected mode of operation.

Claim 21

A variable length code processor as defined in claim 17, wherein said mode selector comprises: a microprocessor; a coding table memory for storing said variable length coding table; and a decoding table memory for storing said variable length decoding table, wherein said microprocessor selects either the coding table memory or the decoding table memory for downloading respective tables stored therein into said table memory.

Claim 22

A variable length code processor as defined in claim 18, wherein said coding table memory and said decoding table memory are non-volatile memories.

Claim 23

A variable length code processor as defined in claim 17, wherein said table memory is rewritable.