Semiconductor integrated circuit having DRAM mounted on semiconductor chip

Claim 2

A semiconductor integrated circuit having a random ccess memory (DRAM), comprising: a central processing unit (CPU) for controlling and performing various types of operations; a DRAM for storing and outputting data items; a bus controller comprising refresh control means comprising: forced refresh request means for setting an optional interval of a refresh time for the DRAM; and refresh request stop means for forcibly stopping output of a refresh request from the forced refresh request means, and an internal bus group for electrically connecting the CPU, the DRAM, and the bus controller to each other, wherein the CPU, the DRAM, and the bus controller are on a single semiconductor chip.

Claim 3

A semiconductor integrated circuit having a DRAM on a single semiconductor chip as claimed in claim 1, wherein the forced refresh request means, that may be accessed by executing an instruction by the CPU, comprising a refresh counter for counting a number from a value in the refresh counter that is written by the CPU and for outputting the refresh request at a different timing from a constant time interval, and wherein the refresh request stop means comprising a first register, that may be accessed by executing an instruction by the CPU, stops to output the refresh request from the refresh control means based on a value stored in the first register.

Claim 4

A semiconductor integrated circuit having a DRAM on a single semiconductor chip as claimed in claim 1, wherein the forced refresh request means comprising a second register, that may be accessed by executing an instruction by the CPU, for outputting the refresh request at a different timing that is different from a constant time interval based on the value from the second register, and wherein the refresh request stop means comprising a first register, that may be accessed by executing an instruction by the CPU, for halting to output the refresh request based on a value stored in the first register.

Claim 5

A semiconductor integrated circuit having a DRAM on a single semiconductor chip as claimed in claim 1, wherein the forced refresh request means, that may be accessed by executing an instruction by the CPU, comprising a refresh counter for counting a number from a value in the refresh counter that is written by the CPU and for outputting the refresh request at a different timing from a constant time interval, and wherein the operation of the refresh request stop means may be controlled by an external device through an external terminal.

Claim 6

A semiconductor integrated circuit having a DRAM on a single semiconductor chip as claimed in claim 1, wherein the forced refresh request means comprising a register, that may be accessed by executing an instruction by the CPU, for outputting the refresh request at a different timing that is different from a constant time interval based on a value from the second register, and wherein the operation of the refresh request stop means may be controlled by an external device through an external terminal.

Claim 7

A semiconductor integrated circuit having a random access memory (DRAM), comprising: a central processing unit (CPU) for controlling and performing various types of operations; a DRAM for storing and outputting data items; a bus controller comprising: refresh control means comprising: forced refresh request means for setting an optional interval of a refresh time for the DRAM; and refresh request stop means for forcibly stopping output of a refresh request from the forced refresh request means, and page mode stop means for halting to output a page mode request signal to the DRAM, and an internal bus group for electrically connecting the CPU, the DRAM, and the bus controller to each other, wherein the CPU, the DRAM, and the bus controller are on a single semiconductor chip.

Claim 8

A semiconductor integrated circuit having a random access memory (DRAM), comprising: a central processing unit (CPU) for controlling and performing various types of operations; a DRAM for storing and outputting data items; a bus controller comprising: refresh control means comprising: forced refresh request means for setting an optional interval of a refresh time for the DRAM; and refresh request stop means for forcibly stopping output of a refresh request from the forced refresh request means, and page mode stop means for halting to output a page mode request signal to the DRAM, and an internal bus group for electrically connecting the CPU, the DRAM, and the bus controller to each other, wherein the CPU, the DRAM, and the bus controller are on a single semiconductor chip.

Claim 9

A semiconductor integrated circuit having a DRAM on a single semiconductor chip as claimed in claim 6, wherein the page mode stop means for halting to access the page mode comprising a page mode stop register, that may be accessed by executing an instruction by the CPU, and means for controlling to access the page mode, based on a value of the page mode stop register.

Claim 10

A semiconductor integrated circuit having a DRAM on a single semiconductor chip as claimed in claim 6, wherein the page mode stop means comprises means, for controlling to access the page mode, that may be accessed by an external device through an external terminal.