US5933047A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage generating circuit for volatile semiconductor memories
Assignee: Nvidia Corp
•
Filing: 1997-04-30
•
Granted: 1999-08-03
•
Expires: 2017-04-30
Abstract
Abstract A high voltage generating circuit which provides a constant V PP output without any threshold voltage drop and which does not suffer from latch-up problems is described. Thus a voltage boosting circuit which provides for a boosted voltage V PP at an output node, from a supply voltage V DD , includes a precharge transistor element responsive to a precharge clock signal for transferring the supply voltage V DD to a boost node for precharging the boost node to the full supply voltage V DD . The circuit further includes a capacitive element connected between the boost node and a pump node, the capacitive element pumping the boost node in response to a pump voltage signal applied to the pump node; and a switching element connected between the boost node and the output node, for transferring charge from the capacitive element to the output node to provide the boosted voltage V PP . In particular the precharge transistor element is an PMOS transistor. Furthermore in order to prevent latch-up of the PMOS devices, a switching circuit is provided to maintain the substrate at the highest voltage in the circuit.
Inventors
- 👤 Jieyan Zhu
- 👤 Valerie Lines
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:53
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; G; G11; G11C; G11C5/00; G11C5/14; G11C5/145; H02; H02M; H02M3/00; H02M3/02; H02M3/04; H02M3/06; H02M3/07; H02M3/073; H03K17/00; H03K17/08; H03K17/081; H03K17/08104
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
167 words
A voltage boosting circuit for providing a boosted voltage V PP at an output node, from a supply voltage V DD , said circuit comprising: a) a precharge transistor element responsive to a precharge clock signal for transferring said supply voltage V DD to a boost node for precharging said boost node to said fill supply voltage V DD , said precharge transistor having its local substrate connected to a biasing node; b) a capacitive element connected between said boost node and a pump node, said capacitive element pumping said boost node in response to a pump voltage signal applied to said pump node; c) a switching element connected between said boost node and said output node, for transferring charge from said capacitive element to said output node to provide said boosted voltage V PP ; and d) a biasing circuit for maintaining said biasing node at a higher one of said V DD and V PP voltages, whereby latch-up of said precharge transistor element is prevented.
Claim 2
Dependent Claim
167 words
A voltage boosting circuit for providing a boosted voltage V PP at an output node, from a supply voltage V DD , said circuit comprising: a) a precharge transistor element responsive to a precharge clock signal for transferring said supply voltage V DD to a boost node for precharging said boost node to said fill supply voltage V DD , said precharge transistor having its local substrate connected to a biasing node; b) a capacitive element connected between said boost node and a pump node, said capacitive element pumping said boost node in response to a pump voltage signal applied to said pump node; c) a switching element connected between said boost node and said output node, for transferring charge from said capacitive element to said output node to provide said boosted voltage V PP ; and d) a biasing circuit for maintaining said biasing node at a higher one of said V DD and V PP voltages, whereby latch-up of said precharge transistor element is prevented.
Claim 3
Dependent Claim
15 words
A circuit as defined in claim 1, said precharge transistor element being an PMOS transistor.
Claim 4
Dependent Claim
14 words
A circuit as defined in claim 1, said switching element being an PMOS transistor.
Claim 5
Dependent Claim
46 words
A circuit as defined in claim 1, said substrate biasing circuit including a substrate switching circuit responsive to a switching signal for selectively connecting said substrate biasing node to a higher voltage of either said boosted voltage V PP or said supply voltage V DD .
Claim 6
Dependent Claim
17 words
A circuit as defined in claim 4, including a voltage comparator means for generating said switching signal.
Claim 7
Dependent Claim
32 words
A circuit as defined in claim 1, including a second capacitive element connected between said substrate biasing node and said supply voltage, for coupling charge between said supply and said biasing node.
Claim 8
Dependent Claim
44 words
A circuit as defined in claim 1, including a diode element connected between said supply voltage V DD and said output node, for directly charging said output node when said output node is at a voltage less than said supply voltage V DD .
Claim 9
Dependent Claim
34 words
A circuit as defined in claim 7, said diode element being an NMOS transistor, having its gate-drain terminals connected to said supply voltage V DD and its source terminal connected to said output node.
Claim 10
Dependent Claim
17 words
A circuit as defined in claim 1, said precharge signal being a V PP level oscillating signal.
Claim 11
Dependent Claim
18 words
A circuit as defined in claim 1, said pump voltage signal being a V DD level oscillating signal.
Claim 12
Dependent Claim
17 words
A circuit as defined in claim 3, said switching element transistor being responsive to a transfer signal.
Claim 13
Dependent Claim
17 words
A circuit as defined in claim 11, said transfer signal being a V PP level oscillating signal.
Claim 14
Dependent Claim
218 words
A circuit as defined in claim 5, said voltage comparator means including a) an first output node for outputting said switching signal; b) a first current path defined between a first input node and a ground node, said first input node for coupling said supply voltage V dd thereto; c) a second current path defined between a second input node and said ground node, said second input node for coupling said boosted voltage V PP thereto; d) a first driver element connected to said first input node in said first current path; e) a second driver element connected between said second input node and said first output node in said second current path; f) a first load element connected in said first current path; g) a second load element connected in said second current path between said first output node and said ground node; said first and second load element being coupled such that currents through said first and second load elements and said first driver elements are equal; and whereby said first output node is driven high upon said current in said first current path being less than current through said second driver and said first output being driven low upon said current in said first current path being greater than current through said second driver element.
Claim 15
Dependent Claim
33 words
A circuit as defined in claim 13, said voltage comparator including a power saving means for reducing current in said first and second current paths when said boost voltage exceeds said supply voltage.
Claim 16
Dependent Claim
22 words
A circuit as defined in claim 13, said voltage comparator including initialization means for initializing voltages in said comparator circuit upon power-up.
Claim 17
Dependent Claim
185 words
A voltage boosting circuit for providing a boosted voltage V PP at an output node, from a supply voltage V DD , said circuit comprising a) a PMOS precharge transistor element responsive to a precharge clock signal for transferring said supply voltage V DD to a boost node for precharging said boost node to said full supply voltage V DD ; b) a capacitive element connected between said boost node and a pump node, said capacitive element pumping said boost node in response to a pump voltage signal applied to said pump node; c) a PMOS transistor switching element connected between said boost node and said output node, for transferring charge from said capacitive element to said output node to provide said boosted voltage V PP ; and d) said PMOS transistor elements having their substrates connected to a biasing node and including a substrate switching circuit responsive to a switching signal for selectively connecting said substrate biasing node to a higher voltage of either said boosted voltage V PP or said supply voltage V DD , whereby latch-up of said PMOS transistors is prevented.
Claim 18
Dependent Claim
185 words
A voltage boosting circuit for providing a boosted voltage V PP at an output node, from a supply voltage V DD , said circuit comprising a) a PMOS precharge transistor element responsive to a precharge clock signal for transferring said supply voltage V DD to a boost node for precharging said boost node to said full supply voltage V DD ; b) a capacitive element connected between said boost node and a pump node, said capacitive element pumping said boost node in response to a pump voltage signal applied to said pump node; c) a PMOS transistor switching element connected between said boost node and said output node, for transferring charge from said capacitive element to said output node to provide said boosted voltage V PP ; and d) said PMOS transistor elements having their substrates connected to a biasing node and including a substrate switching circuit responsive to a switching signal for selectively connecting said substrate biasing node to a higher voltage of either said boosted voltage V PP or said supply voltage V DD , whereby latch-up of said PMOS transistors is prevented.
Claim 19
Independent Claim
161 words
A method of providing a boosted voltage V PP at an output node, from a supply voltage V DD , said method comprising the steps of: a) precharging a boost node to said full supply voltage V DD with a precharge transistor element responsive to a precharge clock signal for transferring said supply voltage V DD to said boost node said precharge transistor element having its local substrate connected to a biasing node; b) pumping said boost node with a capacitive element connected between said boost node and a pump node, in response to a pump voltage signal applied to said pump node; c) transferring charge from said capacitive element to said output node to provide said boosted voltage V PP with a switching element connected between said boost node and said output node; and d) maintaining said biasing node at a higher one of said V DD and V PP voltages, whereby latch-up of said precharge transistor element is prevented.
Claim 20
Independent Claim
161 words
A method of providing a boosted voltage V PP at an output node, from a supply voltage V DD , said method comprising the steps of: a) precharging a boost node to said full supply voltage V DD with a precharge transistor element responsive to a precharge clock signal for transferring said supply voltage V DD to said boost node said precharge transistor element having its local substrate connected to a biasing node; b) pumping said boost node with a capacitive element connected between said boost node and a pump node, in response to a pump voltage signal applied to said pump node; c) transferring charge from said capacitive element to said output node to provide said boosted voltage V PP with a switching element connected between said boost node and said output node; and d) maintaining said biasing node at a higher one of said V DD and V PP voltages, whereby latch-up of said precharge transistor element is prevented.
References Cited (Backward Citations)
US5196996A
Cited
US5157279A
Cited
US5126590A
Cited
US5557231A
Cited
US5394365A
Cited
US5633825A
Cited
US5568065A
Cited
US5521546A
Cited
US5521871A
Cited
US5594381A
Cited
US5748032A
Cited
US5790393A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-02 | 2003-02-01 | 2003-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-02 | 2007-02-01 | 2007-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-02 | 2011-02-01 | 2011-08-03 | $7700.00 | Window Closed / Lapsed |