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US5930599A
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US
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Semiconductor device and method of manufacturing the same
Assignee: Adeia Semiconductor Advanced Technologies Inc
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Filing: 1998-03-18
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Granted: 1999-07-27
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Expires: 2018-03-18
Abstract
Abstract A semiconductor device comprises a square-shaped first semiconductor chip having a first LSI, a square-shaped second semiconductor chip having a second LSI, which is smaller in size than the first semiconductor chip and connected to the first semiconductor chip by face down bonding, and a square-shaped package made of a molding resin for packaging the first and second semiconductor chips. The respective centers of the first and second semiconductor chips are offset from each other, while the center of the second semiconductor chip is substantially coincident with the center of the molding resin.
Inventors
- 👤 Hiroaki Fujimoto
- 👤 Shinitsu Takehashi
- 👤 Takashi Ohtsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:33
CPC Classifications
H; H10; H10W; H10W90/00; H10W70/00; H10W70/40; H10W70/479; H10W74/00; H10W74/01; H10W74/012; H10W74/014; H10W74/10; H10W74/111; H10W74/121; H10W74/15; H10W72/00; H10W72/01; H10W72/0198; H10W72/071; H10W72/072; H10W72/073; H10W72/07331; H10W72/07337; H10W72/07338; H10W72/20; H10W72/241; H10W72/30; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/851; H10W72/853; H10W72/856; H10W72/874; H10W72/884; H10W90/20; H10W90/284; H10W90/291; H10W90/701; H10W90/721; H10W90/722; H10W90/731; H10W90/732; H10W90/736; H10W90/751; H10W90/754; H10W90/756
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
161 words
A method of manufacturing a semiconductor device, comprising: a chip connecting step of connecting, by face down bonding, a first semiconductor chip having a first LSI to a second semiconductor chip having a second LSI, said second semiconductor chip being smaller in size than said first semiconductor chip; and a chip packaging step of packaging said first and second semiconductor chips connected to each other in a package, wherein said chip connecting step includes the step of connecting said first semiconductor chip to said second semiconductor chip such that the center of said first semiconductor chip is offset from the center of said second semiconductor chip in a first direction in which a first one of two contiguous edges of said second semiconductor chip extends, said first edge being as long as or shorter than the other one of the two contiguous edges, and that the center of said second semiconductor chip is substantially coincident with the center of said package.
Claim 2
Independent Claim
161 words
A method of manufacturing a semiconductor device, comprising: a chip connecting step of connecting, by face down bonding, a first semiconductor chip having a first LSI to a second semiconductor chip having a second LSI, said second semiconductor chip being smaller in size than said first semiconductor chip; and a chip packaging step of packaging said first and second semiconductor chips connected to each other in a package, wherein said chip connecting step includes the step of connecting said first semiconductor chip to said second semiconductor chip such that the center of said first semiconductor chip is offset from the center of said second semiconductor chip in a first direction in which a first one of two contiguous edges of said second semiconductor chip extends, said first edge being as long as or shorter than the other one of the two contiguous edges, and that the center of said second semiconductor chip is substantially coincident with the center of said package.
Claim 3
Dependent Claim
96 words
A method of manufacturing a semiconductor device according to claim 1, wherein said chip connecting step includes the step of connecting said first semiconductor chip to said second semiconductor chip such that the center of said first semiconductor chip is offset from the center of said second semiconductor chip in a second direction in which a second one of the two contiguous edges of said second semiconductor chip extends, said second edge being different from said first edge, and that the center of said second semiconductor chip is substantially coincident with the center of said package.
Claim 4
Independent Claim
226 words
A method of manufacturing a semiconductor device composed of a first semiconductor chip having a first LSI and a second semiconductor chip having a second LSI, said second semiconductor chip being smaller in size than said first semiconductor chip and connected to said first semiconductor chip by face down bonding, said method comprising; a first chip separating step of dicing a semiconductor wafer on which a plurality of second semiconductor chips are formed and separating said plurality of second semiconductor chips from each other; a chip connecting step of individually connecting, by face down bonding, said plurality of second semiconductor chips separated from each other to a plurality of first semiconductor chips formed on a semiconductor wafer; a resin filling step of filling an insulating resin in each of the spaces between said plurality of first semiconductor chips and said plurality of second semiconductor chips connected to each other a chip polishing step of polishing the faces of said second semiconductor chips on the other side of the faces thereof opposed to said first semiconductor chip; and a second chip separating step of dicing the semiconductor wafer on which said plurality of first semiconductor chips are formed and separating said plurality of first semiconductor chips from each other, wherein said chip polishing step is performed between said resin filling step and said second chip separating step.
Claim 5
Independent Claim
226 words
A method of manufacturing a semiconductor device composed of a first semiconductor chip having a first LSI and a second semiconductor chip having a second LSI, said second semiconductor chip being smaller in size than said first semiconductor chip and connected to said first semiconductor chip by face down bonding, said method comprising; a first chip separating step of dicing a semiconductor wafer on which a plurality of second semiconductor chips are formed and separating said plurality of second semiconductor chips from each other; a chip connecting step of individually connecting, by face down bonding, said plurality of second semiconductor chips separated from each other to a plurality of first semiconductor chips formed on a semiconductor wafer; a resin filling step of filling an insulating resin in each of the spaces between said plurality of first semiconductor chips and said plurality of second semiconductor chips connected to each other a chip polishing step of polishing the faces of said second semiconductor chips on the other side of the faces thereof opposed to said first semiconductor chip; and a second chip separating step of dicing the semiconductor wafer on which said plurality of first semiconductor chips are formed and separating said plurality of first semiconductor chips from each other, wherein said chip polishing step is performed between said resin filling step and said second chip separating step.
Claim 6
Dependent Claim
52 words
A method of manufacturing a semiconductor device according to claim 3, further comprising, between said resin filling step and said chip polishing step, a resin layer forming step of forming a resin layer surrounding said second semiconductor chips on the faces of said first semiconductor chips opposed to said second semiconductor chips.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |