Patent US5930507A successfully refreshed from Google Patents.
US5930507A
Expired / Lapsed
US
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Compiling processing apparatus
Assignee: Fujitsu Ltd
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Filing: 1996-05-30
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Granted: 1999-07-27
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Expires: 2016-05-30
Abstract
Abstract A compiling processing apparatus which compiles a program operating in a computer having a cache memory. This apparatus collects memory access data for the cache memory, analyzes confliction relationships between them, determines whether or not an instruction for confliction memory access data relocates, relocates the instruction if relocation is possible, and reduces the number of cache miss. Further, this apparatus recognizes memory access data in a continuous area, audits recognized memory access data alignment, generates an instruction of pair-load/pair-store, and reduces the number of memory accesses.
Inventors
- 👤 Tadashi Nakahira
- 👤 Masakazu Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 09:03
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/40; G06F8/41; G06F8/44; G06F8/443; G06F8/4441; G06F8/4442; G06F12/00; G06F12/02; G06F12/08; G06F12/0802
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
174 words
An apparatus for compiling programs for execution in a computer having a cache memory, said apparatus comprising: memory access data collection means for collecting memory access data in an optimization process for compiling a program; confliction data analysis means for analyzing confliction relationships in a cache memory between the collected memory access data; memory access data overlap analysis means for determining, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicting in said cache memory; instruction relocation means for relocating an instruction to eliminate a cache miss for the memory access data conflicting in the cache memory; continuous area generation means for increasing the amount of memory access data for a continuous area by loop unrolling in the optimization process for compiling the program; means for collecting the memory access data after increasing said memory access data for said continuous area by said memory access data collection means; and means for aligning instructions for the memory access data for the continuous area by said instruction relocation means.
Claim 2
Independent Claim
174 words
An apparatus for compiling programs for execution in a computer having a cache memory, said apparatus comprising: memory access data collection means for collecting memory access data in an optimization process for compiling a program; confliction data analysis means for analyzing confliction relationships in a cache memory between the collected memory access data; memory access data overlap analysis means for determining, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicting in said cache memory; instruction relocation means for relocating an instruction to eliminate a cache miss for the memory access data conflicting in the cache memory; continuous area generation means for increasing the amount of memory access data for a continuous area by loop unrolling in the optimization process for compiling the program; means for collecting the memory access data after increasing said memory access data for said continuous area by said memory access data collection means; and means for aligning instructions for the memory access data for the continuous area by said instruction relocation means.
Claim 3
Dependent Claim
60 words
The apparatus according to claim 1, wherein said confliction data analysis means includes means for analyzing confliction relationships in the cache memory between the collected memory access data based on specified architecture information for a computer on which the program is to be run after compilation, whereby confliction data analysis can be performed for plural types of cache memory configurations.
Claim 4
Independent Claim
89 words
An apparatus for compiling a program for execution in a computer having a cache memory, said apparatus comprising: continuous area recognition means for recognizing, in a compile optimization process for the program, memory access data for a continuous area of memory; alignment detecting means for detecting memory access data alignment for the recognized continuous area; and pair-load/pair-store means for generating an instruction for an operation selected from storing and loading plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
Claim 5
Independent Claim
89 words
An apparatus for compiling a program for execution in a computer having a cache memory, said apparatus comprising: continuous area recognition means for recognizing, in a compile optimization process for the program, memory access data for a continuous area of memory; alignment detecting means for detecting memory access data alignment for the recognized continuous area; and pair-load/pair-store means for generating an instruction for an operation selected from storing and loading plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
Claim 6
Independent Claim
193 words
An apparatus for compiling programs for execution in a computer having a cache memory, said apparatus comprising: continuous area generation means for increasing an amount of memory access data for a continuous area by loop unrolling in an optimization process for compiling a program; memory access data collection means for collecting memory access data; confliction data analysis means for analyzing confliction relationships in a cache memory between the collected memory access data; memory access data overlap analysis means for analyzing, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicted in said cache memory; instruction relocation means for relocating instructions to reduce cache misses for the memory access data conflicting in the cache memory based on a memory, access data overlap analysis result; continuous area recognition means for recognizing the memory access data for the continuous area; alignment detecting means for detecting memory access data alignment for the recognized continuous area; and pair-load/pair-store generation means for generating an instruction for an operation selected from loading and storing plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
Claim 7
Independent Claim
193 words
An apparatus for compiling programs for execution in a computer having a cache memory, said apparatus comprising: continuous area generation means for increasing an amount of memory access data for a continuous area by loop unrolling in an optimization process for compiling a program; memory access data collection means for collecting memory access data; confliction data analysis means for analyzing confliction relationships in a cache memory between the collected memory access data; memory access data overlap analysis means for analyzing, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicted in said cache memory; instruction relocation means for relocating instructions to reduce cache misses for the memory access data conflicting in the cache memory based on a memory, access data overlap analysis result; continuous area recognition means for recognizing the memory access data for the continuous area; alignment detecting means for detecting memory access data alignment for the recognized continuous area; and pair-load/pair-store generation means for generating an instruction for an operation selected from loading and storing plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
Claim 8
Independent Claim
143 words
A method of program compiling for a computer having a cache memory, the method comprising the steps of: collecting memory access data in an optimization process for compiling a program; confliction data analysis means for analyzing confliction relationships in a cache memory between the collected memory access data; performing memory access data overlap analysis to determine, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicting in said cache memory; relocating the instruction when a result of the memory access overlap analysis indicates to relocate the instruction; increasing the amount of memory access data for a continuous area by loop unrolling in the optimization process for compiling the program: collecting the memory access data after increasing said memory access data for said continuous area; and aligning instructions for the memory access data for the continuous area.
Claim 9
Independent Claim
143 words
A method of program compiling for a computer having a cache memory, the method comprising the steps of: collecting memory access data in an optimization process for compiling a program; confliction data analysis means for analyzing confliction relationships in a cache memory between the collected memory access data; performing memory access data overlap analysis to determine, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicting in said cache memory; relocating the instruction when a result of the memory access overlap analysis indicates to relocate the instruction; increasing the amount of memory access data for a continuous area by loop unrolling in the optimization process for compiling the program: collecting the memory access data after increasing said memory access data for said continuous area; and aligning instructions for the memory access data for the continuous area.
Claim 10
Independent Claim
73 words
A method of program compiling for a computer having a cache memory, comprising the steps of: recognizing memory access data for a continuous area in a compile optimization process for a program; detecting memory access data alignment for the recognized continuous area; and generating an instruction for an operation selected from storing and loading plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
Claim 11
Independent Claim
73 words
A method of program compiling for a computer having a cache memory, comprising the steps of: recognizing memory access data for a continuous area in a compile optimization process for a program; detecting memory access data alignment for the recognized continuous area; and generating an instruction for an operation selected from storing and loading plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
Claim 12
Independent Claim
139 words
A method of program compiling for a computer having a cache memory, comprising the steps of: increasing an amount of memory access data for a continuous area by loop unrolling in an optimization process for compiling a program; collecting memory access data; analyzing confliction relationships in a cache memory between the collected memory access data; analyzing, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicted in the cache memory; relocating the instruction based on a memory access data overlap analysis result; recognizing the memory access data for the continuous area; detecting memory access data alignment for the recognized continuous area; and generating an instruction for an operation selected from storing and loading plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
Claim 13
Independent Claim
139 words
A method of program compiling for a computer having a cache memory, comprising the steps of: increasing an amount of memory access data for a continuous area by loop unrolling in an optimization process for compiling a program; collecting memory access data; analyzing confliction relationships in a cache memory between the collected memory access data; analyzing, based on a confliction data analysis result, whether to relocate an instruction for memory access data conflicted in the cache memory; relocating the instruction based on a memory access data overlap analysis result; recognizing the memory access data for the continuous area; detecting memory access data alignment for the recognized continuous area; and generating an instruction for an operation selected from storing and loading plural memory access data for the continuous area as one memory access data, based on an alignment detecting result.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |