Photodetector quiescent current compensation method and apparatus

Claim 2

In an integrating capacitor type amplifier having an integration capacitor and a reset switch for periodically, after an integration period during which the capacitor is charging to a voltage, discharging the integration capacitor and having discharged the capacitor allowing it to recharge during a succeeding integration period, the amplifier for use with a photodetector having a photodetector current comprised of quiescent currents and signal currents generated by sometimes incident optical signals and having the photodetector current charging the integration capacitor to a voltage which is further processed by connected circuitry which saturates when the voltage on the integration capacitor is too high, a method of compensating for the current from the quiescent photodetector comprising the steps of: a) obtaining a sample of the voltage on the integration capacitor at controlled sample times during one or more integration times; b) obtaining an average of one or more of the voltage samples; and c) subtracting current from the photodetector current that is charging the integration capacitor in a monotonicaly increasing amount as the average increases; whereby a feedback loop is formed external to the integrating capacitor type amplifier and the voltage on the integration capacitor for the integration periods at corresponding sample times is kept constant at a desired value.

Claim 3

The method of claim 1 wherein samples are obtained only from integration periods when it is known that no optical signal is present so that the constant desired value of voltage on the integration capacitor is determined only by quiescent currents.

Claim 4

The method of claim 2 wherein the timing of samples is adjusted over a range from the beginning to the end of the integration period so that the voltage at the end of the integration period is controlled so that the range of signal currents when present which will produce a voltage on the integration capacitor at the end of an integration period which is between zero and the saturation voltage is adjusted to be in a range from the most negative value of opposite polarity to the quiescent current to the most positive value of the same polarity, respectively.

Claim 5

The method of claim 1 wherein an approximately equal number of samples are obtained from integration periods when it is known that no optical signal is present and when it is known that optical signals are present so that the constant desired value of voltage on the integration capacitor is determined by an average of quiescent currents and signal currents.

Claim 6

The method of claim 4 wherein the timing of samples is adjusted over a range from the beginning to the end of the integration period so that the voltage on the integration capacitor at the end of the integration period produced by the average value of the quiescent and signal currents can be adjusted, preferably to a value of half the saturation voltage.

Claim 7

The method of claim 1 wherein the number of samples is increased from less than one per integration period to more than one per integration period until a desired feedback loop phase margin is achieved.

Claim 8

In an integrating capacitor type amplifier having an integration capacitor and a controllable reset switch for periodically, after an integration period during which the capacitor is charging to a voltage, discharging the integration capacitor and having discharged the capacitor allowing it to recharge during a succeeding integration period, the amplifier for use with a photodetector having a photodetector current comprised of a quiescent current and signal currents generated by sometimes incident optical signals and having the photodetector current charging the integration capacitor to a voltage which is further processed by connected circuitry which saturates when the voltage on the integration capacitor is too high, an apparatus for compensation of the quiescent current from the photodetector comprising: a) a sampler in electrical communication with the integration capacitor for obtaining a sample of the voltage on the integration capacitor at controlled sample times during one or more integration periods and having a sampler control signal connection; b) an averager in electrical communication with the sampler for obtaining an average of one or more of the voltage samples and having an averager control signal connection; c) timing circuitry in electrical communication with the controls of the reset switch, averager, and sampler and capable of generating separate control signals for each; and d) a controlled current source having a control port in electrical communication with the averager output and having an output port in electrical communication with the integrating capacitor type amplifier for subtracting current from the photodetector current that is charging the integration capacitor in a monotonically increasing amount as the average increases; whereby a feedback loop is formed external to the integrating capacitor type amplifier and the voltage on the integration capacitor for the integration periods at corresponding sample times is kept constant at a desired value.

Claim 9

In an integrating capacitor type amplifier having an integration capacitor and a controllable reset switch for periodically, after an integration period during which the capacitor is charging to a voltage, discharging the integration capacitor and having discharged the capacitor allowing it to recharge during a succeeding integration period, the amplifier for use with a photodetector having a photodetector current comprised of a quiescent current and signal currents generated by sometimes incident optical signals and having the photodetector current charging the integration capacitor to a voltage which is further processed by connected circuitry which saturates when the voltage on the integration capacitor is too high, an apparatus for compensation of the quiescent current from the photodetector comprising: a) a sampler in electrical communication with the integration capacitor for obtaining a sample of the voltage on the integration capacitor at controlled sample times during one or more integration periods and having a sampler control signal connection; b) an averager in electrical communication with the sampler for obtaining an average of one or more of the voltage samples and having an averager control signal connection; c) timing circuitry in electrical communication with the controls of the reset switch, averager, and sampler and capable of generating separate control signals for each; and d) a controlled current source having a control port in electrical communication with the averager output and having an output port in electrical communication with the integrating capacitor type amplifier for subtracting current from the photodetector current that is charging the integration capacitor in a monotonically increasing amount as the average increases; whereby a feedback loop is formed external to the integrating capacitor type amplifier and the voltage on the integration capacitor for the integration periods at corresponding sample times is kept constant at a desired value.

Claim 10

The apparatus of claim 7 wherein the timing circuitry causes the sampler to obtain samples of the voltage on the integration capacitor at controlled times during integration periods when it is known that no optical signals are present so that the constant desired value of voltage on the integration capacitor is determined only by quiescent currents.

Claim 11

The apparatus of claim 8 wherein the timing circuitry causes the samples of the voltage on the integration capacitor to be obtained over a range from the beginning to the end of the integration period so that the range of signal currents when present which will produce a voltage on the integration capacitor at the end of an integration period which is between zero and the saturation voltage is adjusted to be in a range from the most negative value of opposite polarity to the quiescent current to the most positive value of the same polarity, respectively.

Claim 12

The apparatus of claim 7 wherein the timing circuitry causes an approximately equal number of samples to be obtained from integration periods when it is known that no optical signal is present and when it is known that optical signals are present so that the constant desired value of voltage on the integration capacitor is determined by an average of quiescent currents and signal currents.

Claim 13

The apparatus of claim 10 wherein the timing circuitry causes samples to be obtained over a range from the beginning to the end of the integration period so that the voltage on the integration capacitor at the end of the integration period produced by the average value of the quiescent and signal currents can be adjusted, preferably to a value of half the saturation voltage.

Claim 14

The apparatus of claim 7 wherein the timing circuitry causes the number of samples to be increased from less than one per integration period to more than one per integration period until a desired feedback loop phase margin is achieved.

Claim 15

The apparatus of claim 7 wherein: a) the sampler comprises a transistor single pole on/off switch with one side in electrical communication with the integration capacitor and a sampling capacitor in electrical communication with the other side of the switch; b) the averager comprises a transistor single pole on/off switch with one side in electrical communication with the sampling capacitor and an averaging capacitor in electrical communication with the other side of the switch; and c) the controlled current source comprises a transistor current source having a control port in electrical communication with the averaging capacitor, an input port in electrical communication with a voltage power supply, and a current source output port in electrical communication with the integration capacitor, whereby a feedback loop is formed external to the integrating capacitor type amplifier and the voltage on the integration capacitor for the integration periods at corresponding sample times is kept constant at a desired value.

Claim 16

The apparatus of claim 13 wherein the ratio of averaging capacitor value to sampling capacitor value is selected to provide a stable feedback loop at low frequencies.

Claim 17

The apparatus of claim 13 wherein the transistors are MOSFETs.

Claim 18

The apparatus of claim 13 wherein the controlled current source is a MOSFET selected to have as low a transconductance as possible but no lower than the quotient of the maximum current expected from the photodetector and the maximum value of the voltage on the integration capacitor before the connected circuitry saturates, whereby the noise due to the controlled current source is minimized and the average value on the integration capacitor can be controlled to be no larger than the circuit saturation voltage.

Claim 19

An integrated circuit for amplifying signals from one or more photodetectors having an integrating capacitor type amplifier in electrical communication with each photodetector, the amplifier comprising an integration capacitor and a reset switch with an externally connected control port for periodically, after an integration time during which the integration capacitor is charged to a voltage by current from the photodetector, discharging the integration capacitor and having discharged the capacitor allowing it to recharge during a succeeding integration period, the improvement comprising: a) providing a sampling switch to momentarily place the integration capacitor in electrical communication with a sampling capacitor and having a control port for electrical communications external to the integrated circuit; b) providing an averager switch to momentarily place the sampling capacitor in electrical communication with an averaging capacitor and having a control port for electrical communications external to the integrated circuit; and c) providing a transistor current source having a control port in electrical communication with the averaging capacitor, an input port in electrical communication with a voltage supply, and a current source output port in electrical communication with the integration capacitor, whereby external timing circuitry can be used to control the reset switch, sampling switch, and averager switch thereby forming a feedback loop external to the integrating capacitor type amplifier so that the voltage on the integration capacitor at determinable times within the integration periods can be kept constant at a desired value.

Claim 20

An integrated circuit for amplifying signals from one or more photodetectors having an integrating capacitor type amplifier in electrical communication with each photodetector, the amplifier comprising an integration capacitor and a reset switch with an externally connected control port for periodically, after an integration time during which the integration capacitor is charged to a voltage by current from the photodetector, discharging the integration capacitor and having discharged the capacitor allowing it to recharge during a succeeding integration period, the improvement comprising: a) providing a sampling switch to momentarily place the integration capacitor in electrical communication with a sampling capacitor and having a control port for electrical communications external to the integrated circuit; b) providing an averager switch to momentarily place the sampling capacitor in electrical communication with an averaging capacitor and having a control port for electrical communications external to the integrated circuit; and c) providing a transistor current source having a control port in electrical communication with the averaging capacitor, an input port in electrical communication with a voltage supply, and a current source output port in electrical communication with the integration capacitor, whereby external timing circuitry can be used to control the reset switch, sampling switch, and averager switch thereby forming a feedback loop external to the integrating capacitor type amplifier so that the voltage on the integration capacitor at determinable times within the integration periods can be kept constant at a desired value.

Claim 21

The integrated circuit defined in claim 17 wherein the ratio of the values of the averaging to sampling capacitors is selected to provide a stable feedback loop stability at low frequencies.

Claim 22

The integrated circuit of 17 wherein the controlled current source is a MOSFET selected to have as low a transconductance as possible but no lower than the quotient of the maximum current expected from the photodetector and the maximum value of the voltage on the integration capacitor before the connected circuitry saturates, whereby the noise due to the controlled current source is minimized and the average value on the integration capacitor can be controlled to be no larger than the circuit saturation voltage.

Claim 23

The integrated circuit of 17 wherein the controlled current source is a MOSFET selected to have as low a transconductance as possible but no lower than the quotient of the maximum current expected from the photodetector and the maximum value of the voltage on the integration capacitor before the connected circuitry saturates, whereby the noise due to the controlled current source is minimized and the average value on the integration capacitor can be controlled to be no larger than the circuit saturation voltage.