Peripheral card security and configuration interface

Claim 2

Peripheral apparatus for use with a base unit, comprising: a connector via which said peripheral apparatus is attachable to said base unit, said connector carrying a plurality of signal lines forming a bus, one of said signal lines carrying a security output from said peripheral apparatus; a code production unit having a code output, said code production unit producing a security code on said code output as a serial bit stream at least during authenticity check times; a source of download data, having a data output; and output circuitry coupled to said code output and said data output, said output circuitry coupling said code output to said security output data line during said authenticity check times and coupling said data output to said security output data line during times other than said authenticity check times.

Claim 3

Apparatus according to claim 1, wherein said bus further includes a reset signal line carrying a reset signal to said peripheral apparatus, and wherein said output circuitry is coupled to said reset line and couples said code output to said security output data line when said reset signal is negated and couples said data output to said security output data line when said reset signal is asserted.

Claim 4

Apparatus according to claim 2, wherein said reset line is also coupled to said code production unit, said code production unit resetting to a predetermined state in response to assertion of said reset signal.

Claim 5

Apparatus according to claim 2, wherein said source of download data comprises: a ROM having an address input and said data output; an address counter having a count output coupled to said ROM address input, and further having a reset input; and counter reset circuitry coupled to receive said reset signal and a memory select signal from said bus, and having an output coupled to said reset input of said counter, said counter reset circuitry resetting said counter in response to assertion of said reset signal together with said additional signal being at a predetermined logic level.

Claim 6

Apparatus according to claim 1, wherein said bus includes address lines, data lines and control lines, wherein said code production unit is coupled to said bus including at least a particular one of collectively said address and data lines, said code production unit producing said security code as a predetermined function of a sequence of signals received from said bus, said security code being responsive at least to said particular signal.

Claim 7

Apparatus according to claim 5, wherein said bus carries data access cycles generated by said base unit, further comprising a peripheral card functional unit coupled to said bus which responds to at least a subset of said data access cycles.

Claim 8

Apparatus according to claim 5, wherein said bus carries data access cycles generated by said base unit, including data read accesses directed to said peripheral apparatus, further comprising a peripheral card functional unit coupled to said bus which drives data onto said data lines of said bus in response to at least a subset of said data read accesses.

Claim 9

Apparatus according to claim 1, wherein said source of download data comprises a ROM.

Claim 10

Apparatus according to claim 8, wherein said ROM includes an address input and said data output, said source of download data further comprising an address counter having a count output coupled to said address input of said ROM, said address counter being further coupled to said bus to increment said count output in response to each cycle on one of said signal lines on said bus at least during ROM download times.

Claim 11

Apparatus according to claim 9, wherein said bus includes a clock signal line different from said one of said signal lines.

Claim 12

Apparatus according to claim 9, further comprising said base unit.

Claim 13

Apparatus according to claim 9, further comprising said base unit, said base unit comprising: a shift register having a serial input coupled to said security output data line; and clocking circuitry coupled to said bus and to said shift register, said clocking circuitry clocking said shift register in response to each cycle on said one of said signal lines during said ROM download times.

Claim 14

Apparatus comprising a base unit, a peripheral unit, and a bus coupling said base unit to said peripheral unit, said bus including a plurality of bus signal lines including address lines, data lines and control lines, said base unit including: a source of data access cycles communicated to said peripheral unit via said bus; a first code production unit coupled to receive signals from said bus and having a first code output; and a comparator having a first input coupled to receive said first code output and further having a second input and an output, said peripheral unit including: a peripheral card functional unit coupled to receive said access cycles via said bus; a second code production unit coupled to receive signals from said bus and having a second code output; and output circuitry coupled to receive said second code output and further having an output coupled to said second input of said comparator in said base unit, said output circuitry coupling said second code output to said second input of said comparator at least during authenticity check times, wherein said first code production unit is arranged to produce a first code sequence on said first code output as a first predetermined function of a sequence of the signals received from said bus, said first code sequence being responsive to at least a particular signal from collectively said address and data lines, wherein said second code production unit is arranged to produce a second code sequence on said second code output as a second predetermined function of a sequence of the signals received from said bus, said second code sequence being responsive at least to said particular signal from collectively said address and data lines, and wherein said second predetermined function is such that said second code sequence matches said first code sequence when the sequence of signals received from said bus by said second code production unit matches the sequence of signals received from said bus by said first code production unit.

Claim 15

Apparatus comprising a base unit, a peripheral unit, and a bus coupling said base unit to said peripheral unit, said bus including a plurality of bus signal lines including address lines, data lines and control lines, said base unit including: a source of data access cycles communicated to said peripheral unit via said bus; a first code production unit coupled to receive signals from said bus and having a first code output; and a comparator having a first input coupled to receive said first code output and further having a second input and an output, said peripheral unit including: a peripheral card functional unit coupled to receive said access cycles via said bus; a second code production unit coupled to receive signals from said bus and having a second code output; and output circuitry coupled to receive said second code output and further having an output coupled to said second input of said comparator in said base unit, said output circuitry coupling said second code output to said second input of said comparator at least during authenticity check times, wherein said first code production unit is arranged to produce a first code sequence on said first code output as a first predetermined function of a sequence of the signals received from said bus, said first code sequence being responsive to at least a particular signal from collectively said address and data lines, wherein said second code production unit is arranged to produce a second code sequence on said second code output as a second predetermined function of a sequence of the signals received from said bus, said second code sequence being responsive at least to said particular signal from collectively said address and data lines, and wherein said second predetermined function is such that said second code sequence matches said first code sequence when the sequence of signals received from said bus by said second code production unit matches the sequence of signals received from said bus by said first code production unit.

Claim 16

Apparatus according to claim 13, wherein said second code production unit comprises a sequential state machine which includes: a second state register having a second current state output, a second next state input, and a second clock input in response to which said second state register updates said second current state output to values responsive to said second next state input; second combinational next state logic having inputs coupled to receive at least one signal from collectively said bus and said second current state output, and further having outputs coupled to said second next state input; second combinational output logic having inputs coupled to receive at least one signal from collectively said bus and said second current state output, and further having an output being said second code output.

Claim 17

Apparatus according to claim 14, wherein said first code production unit also comprises a sequential state machine which includes: a first state register having a first current state output, a first next state input, and a first clock input in response to which said first state register updates said first current state output to values responsive to said first next state input; first combinational next state logic having inputs coupled to receive at least one signal from collectively said bus and said first current state output, and further having outputs coupled to said first next state input; and first combinational output logic having inputs coupled to receive at least one signal from collectively said bus and said first current state output, and further having an output being said first code output.

Claim 18

Apparatus according to claim 14, wherein said second code production unit further comprises combinational clocking logic having an input port coupled to a subset of said control signal lines, and having an output coupled to said second clock input of said second state register.

Claim 19

Apparatus according to claim 16, wherein said control signal lines include a clock signal line, and wherein said clock signal line is not coupled to said combinational clocking logic.

Claim 20

Apparatus according to claim 14, wherein said second code production unit further comprises clocking circuitry coupled to said bus and to said second clock input of said second state register, said clocking circuitry clocking said second state register no more than once in response to each of said data access cycles.

Claim 21

Apparatus according to claim 13, wherein said comparator comprises only combinational circuitry.

Claim 22

Apparatus according to claim 13, wherein said comparator comprises an inequality detector.

Claim 23

Apparatus according to claim 13 further comprising means coupled to said output of said comparator for, in response to a non-match indicated on said output of said comparator, inhibiting said source of data access cycles from initiating further data access cycles until a predefined correcting event occurs.

Claim 24

Apparatus according to claim 13, wherein said particular signal is a signal from said data lines.

Claim 25

Apparatus according to claim 13, wherein said particular signal is a signal from said address lines.

Claim 26

Apparatus according to claim 13, wherein said bus includes a connector by which said peripheral unit is physically and detachably attached to said base unit.

Claim 27

Apparatus according to claim 24, wherein said output circuitry comprises a conductor connecting said peripheral unit to said base unit through said connector.

Claim 28

Apparatus according to claim 13, wherein said output circuitry comprises a multiplexer having a first input port coupled to said second code output and further having an output coupled to said second input of said comparator in said base unit, said multiplexer further having a second input port and a select input, and wherein said peripheral unit further comprises: a source of download data coupled to said second input port of said multiplexer; and means coupled to said select input of said multiplexer, for causing said multiplexer to select said first input port during authenticity check times.

Claim 29

Apparatus according to claim 13, wherein said control signal lines include a card reset signal line, wherein said output circuitry comprises a multiplexer having a first input port coupled to said second code output and further having an output coupled to said second input of said comparator in said base unit, said multiplexer further having a select input port coupled to said card reset signal line and said multiplexer further having a second input port, and wherein said peripheral unit further comprises a source of download data coupled to said second input port of said multiplexer.

Claim 30

Apparatus according to claim 27, wherein said source of download data comprises a ROM in said peripheral unit.

Claim 31

Apparatus according to claim 28, wherein said control signal lines further include a card enable line connected to said peripheral card functional unit, wherein said ROM has an address input port; and wherein said peripheral unit further comprises an address counter having a clock input coupled to said card enable line and further having a count output coupled to said ROM address input port.

Claim 32

Apparatus according to claim 27, wherein said card reset line is further coupled to said second code production unit, said second code production unit resetting to a predetermined state in response to sampling a signal asserted on said card reset line.