Patent US5926786A successfully refreshed from Google Patents.
US5926786A
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Application specific integrated circuit (ASIC) for performing rapid speech compression in a mobile telephone system
Assignee: Qualcomm Inc
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Filing: 1997-06-11
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Granted: 1999-07-20
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Expires: 2017-06-11
Abstract
Abstract A method and apparatus for implementing a vocoder in a application specific integrated circuit (ASIC) is described. The apparatus contains a DSP core that performs computations in accordance with a reduced instruction set (RISC) architecture. The circuit further includes a specifically designed slave processor to the DSP core referred to as the minimization processor. The apparatus further includes a specifically designed block normalization circuitry.
Inventors
- 👤 John G. McDonough
- 👤 Way-Shing Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:57
CPC Classifications
G; G10; G10L; G10L13/00; G06; G06F; G06F5/00; G06F5/01; G10L19/00; G10L19/04; G10L19/06; G10L19/07; G10L19/16; G10L2019/0001; G10L2019/0011; G10L2019/0013
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
94 words
A digital signal processor for performing a filtering operation, said processor generating a plurality of filtering results during a clock cycle, comprising: a first multiply/accumulate element for receiving input signal samples and filter coefficients and for generating a first filtering result; a plurality of additional multiply/accumulate elements; and a control element for placing said plurality of additional multiply/accumulate elements in a filter mode, wherein in said filter mode, said additional multiply/accumulate elements receive delayed versions of said input signal samples and also receive said filter coefficients, and generate a plurality of additional filtering results.
Claim 2
Dependent Claim
94 words
A digital signal processor for performing a filtering operation, said processor generating a plurality of filtering results during a clock cycle, comprising: a first multiply/accumulate element for receiving input signal samples and filter coefficients and for generating a first filtering result; a plurality of additional multiply/accumulate elements; and a control element for placing said plurality of additional multiply/accumulate elements in a filter mode, wherein in said filter mode, said additional multiply/accumulate elements receive delayed versions of said input signal samples and also receive said filter coefficients, and generate a plurality of additional filtering results.
Claim 3
Dependent Claim
31 words
The processor of claim 1 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in a minimization processor.
Claim 4
Dependent Claim
38 words
The processor of claim 1 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in a secondary processor coupled to said digital signal processing core.
Claim 5
Dependent Claim
30 words
The processor of claim 1 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in a co-processor.
Claim 6
Dependent Claim
30 words
The processor of claim 1 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in an accelerator.
Claim 7
Dependent Claim
27 words
The processor of claim 1 wherein said control element controls a plurality of multiplexers to configure a set of predetermined data paths when in said filter mode.
Claim 8
Dependent Claim
25 words
The processor of claim 1 further comprising a multiplexer for receiving said additional filtering results and for selecting one of said filtering results as output.
Claim 9
Dependent Claim
55 words
In a vocoder comprising a digital signal processing core and a minimization processor, wherein said minimization processor comprises a plurality of accumulators and a plurality of multipliers, a subsystem comprising: control means for placing said minimization processor in a filter mode; and arithmetic means responsive to said control means for performing a signal analysis operation.
Claim 10
Dependent Claim
55 words
In a vocoder comprising a digital signal processing core and a minimization processor, wherein said minimization processor comprises a plurality of accumulators and a plurality of multipliers, a subsystem comprising: control means for placing said minimization processor in a filter mode; and arithmetic means responsive to said control means for performing a signal analysis operation.
Claim 11
Dependent Claim
14 words
The vocoder of claim 8 wherein said signal analysis operation is a filtering operation.
Claim 12
Dependent Claim
14 words
The vocoder of claim 8 wherein said signal analysis operation is an autocorrelation operation.
Claim 13
Dependent Claim
14 words
The vocoder of claim 8 wherein said signal analysis operation is a cross-correlation operation.
Claim 14
Dependent Claim
91 words
A digital signal processor for performing a signal analysis operation, said processor generating a plurality of analysis results during a clock cycle, comprising: a first multiply/accumulate element for receiving input signal samples and for generating a first analysis result; a plurality of additional multiply/accumulate elements; and a control element for placing said plurality of additional multiply/accumulate elements in a supplementary mode, wherein in said supplementary mode, said additional multiply/accumulate elements receive said input signal samples and delayed versions of said input signal samples, and generate a plurality of supplementary analysis results.
Claim 15
Dependent Claim
91 words
A digital signal processor for performing a signal analysis operation, said processor generating a plurality of analysis results during a clock cycle, comprising: a first multiply/accumulate element for receiving input signal samples and for generating a first analysis result; a plurality of additional multiply/accumulate elements; and a control element for placing said plurality of additional multiply/accumulate elements in a supplementary mode, wherein in said supplementary mode, said additional multiply/accumulate elements receive said input signal samples and delayed versions of said input signal samples, and generate a plurality of supplementary analysis results.
Claim 16
Dependent Claim
31 words
The processor of claim 12 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in a minimization processor.
Claim 17
Dependent Claim
38 words
The processor of claim 12 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in a secondary processor coupled to said digital signal processing core.
Claim 18
Dependent Claim
30 words
The processor of claim 12 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in a co-processor.
Claim 19
Dependent Claim
30 words
The processor of claim 12 wherein said first multiply/accumulate element is disposed in a digital signal processing core and said plurality of additional multiply/accumulate elements is disposed in an accelerator.
Claim 20
Dependent Claim
27 words
The processor of claim 12 wherein said control element controls a plurality of multiplexers to configure a set of predetermined data paths when in said supplementary mode.
Claim 21
Dependent Claim
25 words
The processor of claim 12 further comprising a multiplexer for receiving said additional analysis results and for selecting one of said analysis results as output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-19 | 2003-01-18 | 2003-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-19 | 2007-01-18 | 2007-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-19 | 2011-01-18 | 2011-07-20 | $7700.00 | Window Closed / Lapsed |