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US5926435A
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Apparatus for saving power consumption in semiconductor memory devices
Assignee: SK Hynix Inc
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Filing: 1997-12-30
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Granted: 1999-07-20
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Expires: 2017-12-30
Abstract
Abstract A power consumption saving apparatus for semiconductor memory devices such as DRAM's, which is configured to preferentially latch a clock signal and a chip selection signal over other input command signals so that latch circuits for latching the input command signals are controlled in accordance with the clock signal and chip selection signal, thereby saving power consumption occurring in input latches not selected. The apparatus includes an input latch as a latch control circuit for preferentially latching a clock signal and a chip selection signal and outputting the latched signals as a control signal for controlling latch circuits.
Inventors
- 👤 Kee Woo Park
- 👤 Jong Woo Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:37
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1093; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C7/22
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
124 words
A power consumption saving apparatus for a semiconductor memory device including at least one DRAM and a control chip adapted to control an operation of the DRAM, the apparatus comprising: a plurality of input buffers respectively adapted to receive external command signals, a chip selection signal and a clock signal what are generated form the control chip; a plurality of latch means respectively adapted to latch output signals from the input buffers; and latch control means coupled to all the latch means and adapted to receive output signals from those of the input buffers respectively receiving the clock signal and the chip selection signal, thereby generating a control signal for selectively activating the plurality of latch means when the chip selection signal is activated.
Claim 2
Dependent Claim
124 words
A power consumption saving apparatus for a semiconductor memory device including at least one DRAM and a control chip adapted to control an operation of the DRAM, the apparatus comprising: a plurality of input buffers respectively adapted to receive external command signals, a chip selection signal and a clock signal what are generated form the control chip; a plurality of latch means respectively adapted to latch output signals from the input buffers; and latch control means coupled to all the latch means and adapted to receive output signals from those of the input buffers respectively receiving the clock signal and the chip selection signal, thereby generating a control signal for selectively activating the plurality of latch means when the chip selection signal is activated.
Claim 3
Dependent Claim
45 words
The power consumption saving apparatus in accordance with claim 1, wherein; the control signal from the latch control means is applied to each of the latch means in sync with the external command signals respectively applied to the latch means via the associated input buffers.
Claim 4
Dependent Claim
45 words
The power consumption saving apparatus in accordance with claim 2, further comprising: delay means, coupled between each of the input buffers receiving the external command signals and an associated one of the latch means and adapted to delay an output signal from the input buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-19 | 2003-01-18 | 2003-07-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-19 | 2007-01-18 | 2007-07-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-19 | 2011-01-18 | 2011-07-20 | $7700.00 | Window Closed / Lapsed |