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US5925903A Expired / Lapsed US ⏱️ 0.0 years remaining

Field-effect transistors and method of manufacturing the same

Assignee: Panasonic Holdings Corp
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Filing: 1997-12-16
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Granted: 1999-07-20
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Expires: 2017-12-16
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Abstract

Abstract A conductive layer made of n-type GaAs is formed on a semi-insulating substrate made of GaAs. A pair of contact regions made of n + -type GaAs are formed on the conductive layer. A source electrode is formed on the left-hand contact region, while a drain electrode is formed on the right-hand contact region. A gate recessed region is formed in the region of the conductive layer located between the pair of contact regions so that a gate electrode is formed on the gate recessed region. A depressed portion is formed in the gate recessed region of the conductive layer. The wall face of the depressed portion closer to the gate electrode is flush with or protruding from the side face of the gate electrode facing the drain electrode.

Inventors

  • 👤 Junko Iwanaga
  • 👤 Yorito Ota
  • 👤 Tadayoshi Nakatsuka
  • 👤 Hiroyuki Masato
  • 👤 Katsuhiko Kawashima

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 13:57
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/80; H10D30/87; H10D30/877; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/161; H10D64/00; H10D64/01; H10D64/012; H10D64/0124; H10D64/0125

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 114 words
A field-effect transistor comprising: a semiconductor substrate; a conductive layer formed on said semiconductor substrate; a source electrode and a drain electrode formed on respective specified regions of said conductive layer to be in ohmic contact with said conductive layer; a gate electrode formed on a region of said conductive layer located between said source electrode and said drain electrode to form a Schottky junction with said conductive layer; and a trench formed in a region of said conductive layer located between said gate electrode and said drain electrode, wherein said trench includes a plurality of trenches formed in said region of said conductive layer located between said gate electrode and said drain electrode.
Claim 2
Dependent Claim 114 words
A field-effect transistor comprising: a semiconductor substrate; a conductive layer formed on said semiconductor substrate; a source electrode and a drain electrode formed on respective specified regions of said conductive layer to be in ohmic contact with said conductive layer; a gate electrode formed on a region of said conductive layer located between said source electrode and said drain electrode to form a Schottky junction with said conductive layer; and a trench formed in a region of said conductive layer located between said gate electrode and said drain electrode, wherein said trench includes a plurality of trenches formed in said region of said conductive layer located between said gate electrode and said drain electrode.
Claim 3
Dependent Claim 122 words
A field-effect transistor comprising: a semiconductor substrate; a conductive layer formed on said semiconductor substrate; a semiconductor layer formed on said conductive layer; a source electrode and a drain electrode formed on respective specified regions of said semiconductor layer to be in ohmic contact with said semiconductor layer; a gate electrode formed in a region of said semiconductor layer located between said source electrode and said drain electrode to form a Schottky junction with said semiconductor layer; and a trench formed in a region of said semiconductor layer located between said gate electrode and said drain electrode, wherein said trench includes a plurality of trenches formed in said region of said semiconductor layer located between said gate electrode and said drain electrode.
Claim 4
Dependent Claim 122 words
A field-effect transistor comprising: a semiconductor substrate; a conductive layer formed on said semiconductor substrate; a semiconductor layer formed on said conductive layer; a source electrode and a drain electrode formed on respective specified regions of said semiconductor layer to be in ohmic contact with said semiconductor layer; a gate electrode formed in a region of said semiconductor layer located between said source electrode and said drain electrode to form a Schottky junction with said semiconductor layer; and a trench formed in a region of said semiconductor layer located between said gate electrode and said drain electrode, wherein said trench includes a plurality of trenches formed in said region of said semiconductor layer located between said gate electrode and said drain electrode.

References Cited (Backward Citations)

US4961194A Cited
JPH098061A Cited
JPH0982725A Cited
US5821576A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-07-19 2003-01-18 2003-07-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-07-19 2007-01-18 2007-07-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-07-19 2011-01-18 2011-07-20 $7700.00 Window Closed / Lapsed

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