Patent US5923952A successfully refreshed from Google Patents.
US5923952A
Expired / Lapsed
US
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Fusion-bond electrical feed-through
Assignee: Kavlico Corp
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Filing: 1997-07-18
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Granted: 1999-07-13
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Expires: 2017-07-18
Abstract
Abstract A semiconductor device has a flexible structure bonded to a semiconductor substructure to form a cavity. The flexible structure is bonded over a conducting feed-through without the feed-through interfering with a hermetic seal formed by bonding. One embodiment of the device includes depressions that contain edges of a diffused feed-through so that imperfections at the edge of the diffusion do not interfere with bonding. The flexible structure is bonded to elevated areas thus hiding the imperfections. In one embodiment, a first elevated region is surrounded by a second elevated region, and diffusion for the feed-through extends from an active region in the cavity across the first elevated region with edges of the diffusion being between the first and second elevated regions. The flexible structure can thus bond to the first and second elevated regions without interference from the edge of the diffused feed-through. A via through the flexible structure to the first elevated region provides electrical contact with the active region. Another embodiment has either a surface or buried well in a semiconductor structure and extending from an active region in the cavity to a point outside the perimeter of the flexible structure. The well provides a conductive feed-through structure without creating imperfections that would interfere with the bonding that seals the cavity.
Inventors
- 👤 M. Salleh Ismail
- 👤 Raffi M. Garabedian
- 👤 Max E. Nielsen
- 👤 Gary J. Pashby
- 👤 Jeffrey K. K. Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:24
CPC Classifications
B; B81; B81C; B81C1/00; B81C1/00015; B81C1/00261; B81C1/00277; B81C1/00293; B81C1/00301; G; G01; G01L; G01L9/00; G01L9/0041; G01L9/0042; G01L9/0072; G01L9/0073; H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/01; H10W10/021; H10W10/10; H10W10/181; H10W10/20; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W76/00; H10W76/60; B81B; B81B2207/00; B81B2207/09; B81B2207/091; B81B2207/092; B81C2203/00; B81C2203/01; B81C2203/0172; B81C2203/019; B81C2203/03; B81C2203/033; B81C2203/036
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
129 words
A method of making a semiconductor device comprising: shaping a semiconductor structure to form a first elevated area, a second elevated area surrounding the first elevated area, and a depression in between the first and second elevated areas; forming a mask over the semiconductor structure, wherein the mask has an edge in the depression; implanting dopants in the semiconductor structure to form a conductive region covering the first elevated area, wherein edges of the conductive region are in the depression and surrounding the first elevated area; bonding a structure on the first and second elevated areas of the semiconductor structure such that a sealed cavity is formed over the depression containing the edges of the conductive region; and forming a contact through the structure to the first elevated area.
Claim 2
Independent Claim
129 words
A method of making a semiconductor device comprising: shaping a semiconductor structure to form a first elevated area, a second elevated area surrounding the first elevated area, and a depression in between the first and second elevated areas; forming a mask over the semiconductor structure, wherein the mask has an edge in the depression; implanting dopants in the semiconductor structure to form a conductive region covering the first elevated area, wherein edges of the conductive region are in the depression and surrounding the first elevated area; bonding a structure on the first and second elevated areas of the semiconductor structure such that a sealed cavity is formed over the depression containing the edges of the conductive region; and forming a contact through the structure to the first elevated area.
Claim 3
Dependent Claim
29 words
The method of claim 1, wherein the elevated area of the semiconductor structure comprises an oxide layer, and forming the depression comprises forming a depression in the oxide layer.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein implanting ions forms imperfections in the depression, and being in the depression prevents the imperfections from interfering with bonding of the wafer.
Claim 5
Dependent Claim
18 words
The method of claim 3, wherein the depression has a depth greater than a height of the imperfections.
Claim 6
Dependent Claim
16 words
The method of claim 1, wherein the conductive region extends to active regions in the depression.
Claim 7
Independent Claim
76 words
A method of making a semiconductor device, comprising: forming a first well in a semiconductor structure; forming an active region that is in the semiconductor structure and in electrical contact with the first well; bonding a structure to the semiconductor structure to form a sealed cavity containing the active region, wherein the first well extends to a point outside a perimeter of the structure; and electrically connecting circuitry to the active region via the first well.
Claim 8
Independent Claim
76 words
A method of making a semiconductor device, comprising: forming a first well in a semiconductor structure; forming an active region that is in the semiconductor structure and in electrical contact with the first well; bonding a structure to the semiconductor structure to form a sealed cavity containing the active region, wherein the first well extends to a point outside a perimeter of the structure; and electrically connecting circuitry to the active region via the first well.
Claim 9
Dependent Claim
19 words
The method of claim 6, wherein the first well and the active region are of the same conductivity type.
Claim 10
Dependent Claim
43 words
The method of claim 6, further comprising: forming an epitaxial layer overlying the first well, wherein the active region is formed in the epitaxial layer; and forming a second well extending from the active region through the epitaxial layer to the first well.
Claim 11
Dependent Claim
56 words
The method of claim 8, further comprising forming a third well outside the perimeter of the structure, wherein the third well extends through the epitaxial layer to the first well, wherein connecting circuitry to the active region comprises connecting the circuitry to the active region via a conductive path through the third, first, and second wells.
Claim 12
Dependent Claim
39 words
The method of claim 9, wherein the first, second, and third wells are of a first conductivity type, the first well is formed in a substrate, and the substrate and the epitaxial layer are of a second conductivity type.
Claim 13
Dependent Claim
35 words
The method of claim 6, further comprising shaping the semiconductor structure to form an elevated area surrounding an area containing the active region, wherein bonding the structure comprises bonding the structure to the elevated area.
Claim 14
Dependent Claim
37 words
The method of claim 6, wherein the structure comprises a wafer having a depression formed therein, and bonding the structure comprises aligned bonding the wafer to the semiconductor structure so that the depression overlies the active region.
Claim 15
Dependent Claim
19 words
The method of claim 6, wherein forming the active region comprises forming the active region in the first well.
Claim 16
Dependent Claim
10 words
The method of claim 6, wherein bonding comprises fusion bonding.
Claim 17
Independent Claim
125 words
A method of making a semiconductor device, comprising: forming a first well in a substrate, the first well having a first conductivity type and the substrate having a second conductivity type; forming an epitaxial layer on the substrate and the first well, the epitaxial layer having the second conductivity type; forming a second well in the epitaxial layer, the second well communicating with the first well and having the first conductivity type; forming an active region in the epitaxial layer, the active region communicating with the second well and having the first conductivity type; and bonding a structure on the epitaxial layer to form a sealed cavity containing the active region, wherein the first well extends to a point outside a perimeter of the structure.
Claim 18
Independent Claim
125 words
A method of making a semiconductor device, comprising: forming a first well in a substrate, the first well having a first conductivity type and the substrate having a second conductivity type; forming an epitaxial layer on the substrate and the first well, the epitaxial layer having the second conductivity type; forming a second well in the epitaxial layer, the second well communicating with the first well and having the first conductivity type; forming an active region in the epitaxial layer, the active region communicating with the second well and having the first conductivity type; and bonding a structure on the epitaxial layer to form a sealed cavity containing the active region, wherein the first well extends to a point outside a perimeter of the structure.
Claim 19
Dependent Claim
37 words
The method of claim 15, further comprising forming a third well in the epitaxial layer and outside the perimeter of the structure, wherein the third well communicates with the first well and has the first conductivity type.
Claim 20
Dependent Claim
30 words
The method of claim 15, further comprising forming an elevated area surrounding an area containing the active region, wherein bonding the structure comprises bonding the structure to the elevated area.
Claim 21
Dependent Claim
34 words
The method of claim 15, wherein the structure comprises a depression formed therein, and bonding the structure comprises aligned boding the structure on the epitaxial layer such that the depression overlies the active region.
Claim 22
Dependent Claim
22 words
The method of claim 15, additionally comprising connecting circuitry to the third well to form a conductive path to the active region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |