Host processor and coprocessor arrangement for processing platform-independent code

Claim 2

A coprocessor arrangement for processing platform-independent program code, comprising: an expansion bus interface circuit; an instruction cache coupled to the expansion bus interface circuit; a platform-independent code processing unit coupled to the instruction cache; an internal control register coupled to the expansion bus interface circuit and having an input port for providing external access thereto, the control register arranged to provide an operational state for the processing unit; and a program counter register coupled to the expansion bus interface circuit and coupled to the platform-independent code processing unit, the program counter register arranged to store an address of a next platform-independent instruction to be processed.

Claim 3

The coprocessor arrangement of claim 1, wherein the expansion bus interface circuit is a PCI bus interface circuit.

Claim 4

The coprocessor arrangement of claim 1, wherein the platform-independent code processing unit is configured to process Java code.

Claim 5

The coprocessor arrangement of claim 1, wherein the platform-independent code processing unit is configured to process ActiveX controls.

Claim 6

A coprocessor arrangement for process ing platform-independent program code, comprising: interface means for providing access to an expansion bus; instruction cache means coupled to the interface means for providing and controlling cache storage of platform-independent program code; processing means coupled to the instruction cache means for processing platform-independent code; an internal control register coupled to the interface means and having an input port for providing external access thereto, the control register for providing an operational state for the processing means; and a program counter register coupled to the interface means and coupled to the processing means for referencing an address of a next platform-independent instruction to be processed.

Claim 7

A coprocessor arrangement for process ing platform-independent program code, comprising: interface means for providing access to an expansion bus; instruction cache means coupled to the interface means for providing and controlling cache storage of platform-independent program code; processing means coupled to the instruction cache means for processing platform-independent code; an internal control register coupled to the interface means and having an input port for providing external access thereto, the control register for providing an operational state for the processing means; and a program counter register coupled to the interface means and coupled to the processing means for referencing an address of a next platform-independent instruction to be processed.

Claim 8

The coprocessor arrangement of claim 5, wherein the expansion bus interface circuit is a PCI bus interface circuit.

Claim 9

The coprocessor arrangement of claim 5, wherein the control unit is configured to process Java code.

Claim 10

The coprocessor arrangement of claim 5, wherein the control unit is configured to process ActiveX controls.

Claim 11

The coprocessor arrangement of claim 5, filter comprising a first externally accessible control bit coupled to the expansion bus interface circuit for switching the coprocessor between a first state of executing the platform-independent code and a second state of not executing the platform-independent code.

Claim 12

The coprocessor arrangement of claim 9, filter comprising a task-complete register coupled to the expansion bus interface circuit for indicating when the coprocessor has completed a task.

Claim 13

The coprocessor of claim 5, further comprising means, coupled to the expansion bus interface circuit, for indicating an exception condition.

Claim 14

The coprocessor of claim 11, wherein the means for indicating includes a second externally accessible control bit coupled to the expansion bus interface circuit and coupled to the control unit for indicating when the control unit cannot process a particular platform-independent instruction.

Claim 15

The coprocessor of claim 5, wherein the control unit is stack-based.

Claim 16

The coprocessor of claim 13, further comprising a stack cache circuit arrangement coupled to the control unit for caching stack entries referenced by the control unit.

Claim 17

The coprocessor of claim 14, wherein the stack cache circuit arrangement includes: a stack cache memory coupled to the control unit for cache storage of stack entries; and a stack cache controller coupled to the stack cache memory and coupled to the control unit for controlling caching of stack entries.

Claim 18

A computer system, comprising: a local bus; a host processor coupled to the local bus for managing execution of platform-independent code; a memory coupled to the local bus for storing the platform-independent code; an expansion bus bridge coupled to the local bus; an expansion bus coupled to the expansion bus bridge; and a coprocessor coupled to the expansion bus for processing the platform-independent code as directed by the host processor, the coprocessing including, an expansion bus interface circuit; an instruction cache coupled to the expansion bus interface circuit; a platform-independent code processing unit coupled to the instruction cache; an internal control register coupled to the expansion bus interface circuit and having an input port for providing external access thereto, the control register for providing an operational state for the coprocessor; and a program counter register coupled to the expansion bus interface circuit and coupled to the platform-independent code processing unit for referencing an address of a next platform-independent instruction to be executed.

Claim 19

A computer system, comprising: a local bus; a host processor coupled to the local bus for managing execution of platform-independent code; a memory coupled to the local bus for storing the platform-independent code; an expansion bus bridge coupled to the local bus; an expansion bus coupled to the expansion bus bridge; and a coprocessor coupled to the expansion bus for processing the platform-independent code as directed by the host processor, the coprocessing including, an expansion bus interface circuit; an instruction cache coupled to the expansion bus interface circuit; a platform-independent code processing unit coupled to the instruction cache; an internal control register coupled to the expansion bus interface circuit and having an input port for providing external access thereto, the control register for providing an operational state for the coprocessor; and a program counter register coupled to the expansion bus interface circuit and coupled to the platform-independent code processing unit for referencing an address of a next platform-independent instruction to be executed.

Claim 20

The computer system of claim 16, wherein the expansion bus is a PCI bus.

Claim 21

The computer system of claim 16, wherein the platform-independent code processing unit is configured to process Java code.

Claim 22

The computer system of claim 16, wherein the platform-independent code processing unit is configured to process ActiveX controls.

Claim 23

A computer system, comprising: a local bus; a host processor coupled to the local bus for managing execution of platform-independent code; a memory coupled to the local bus for storing the platform-independent code; an expansion bus bridge coupled to the local bus; an expansion bus coupled to the expansion bus bridge; and a coprocessor coupled to the expansion bus for processing the platform-independent code as directed by the host processor, the coprocessing including, interface circuit means for providing access to the expansion bus; instruction cache means coupled to the interface means for providing and controlling cache storage of the platform-independent program code; processing means coupled to the instruction cache for executing the platform-independent code; an internal control register coupled to the interface means and having an input port for providing external access thereto, the control register for providing an operational state for the coprocessor; and a program counter register coupled to the interface means and coupled to the control unit for referencing an address of a next platform-independent instruction to be executed by the processing means.

Claim 24

A computer system, comprising: a local bus; a host processor coupled to the local bus for managing execution of platform-independent code; a memory coupled to the local bus for storing the platform-independent code; an expansion bus bridge coupled to the local bus; an expansion bus coupled to the expansion bus bridge; and a coprocessor coupled to the expansion bus for processing the platform-independent code as directed by the host processor, the coprocessing including, interface circuit means for providing access to the expansion bus; instruction cache means coupled to the interface means for providing and controlling cache storage of the platform-independent program code; processing means coupled to the instruction cache for executing the platform-independent code; an internal control register coupled to the interface means and having an input port for providing external access thereto, the control register for providing an operational state for the coprocessor; and a program counter register coupled to the interface means and coupled to the control unit for referencing an address of a next platform-independent instruction to be executed by the processing means.

Claim 25

The computer system of claim 20, wherein the expansion bus is a PCI bus.

Claim 26

The computer system of claim 20, wherein the control unit is configured to process Java code.

Claim 27

The computer system of claim 20, wherein the control unit is configured to process ActiveX controls.

Claim 28

The computer system of claim 20, wherein the coprocessor further includes a first externally accessible control bit coupled to the expansion bus interface circuit for switching the coprocessor between a first state of executing the platform-independent code and a second state of not executing the platform-independent code.

Claim 29

The computer system of claim 20, wherein the coprocessor further includes a task-complete register coupled to the expansion bus interface circuit for indicating when the coprocessor has completed a task.

Claim 30

The computer system of claim 20, wherein the coprocessor further includes means, coupled to the expansion bus interface circuit, for indicating an exception condition.

Claim 31

The computer system of claim 26, wherein the means for indicating includes a second externally accessible control bit coupled to the expansion bus interface circuit and coupled to the control unit for indicating when the control unit cannot process a particular platform-independent instruction.

Claim 32

The computer system of claim 20, wherein the control unit is stack-based.

Claim 33

The computer system of claim 24, wherein the coprocessor further includes a stack cache circuit arrangement coupled to the control unit for caching stack entries referenced by the control unit.

Claim 34

The computer system of claim 25, wherein the stack cache circuit arrangement includes: a stack cache memory coupled to the control unit for cache storage of stack entries; and a stack cache controller coupled to the stack cache memory and coupled to the control unit for controlling caching of stack entries.

Claim 37

The method of claim 31, wherein the transmitting step (c) includes the step of transmitting the activation signal to a PCI bridge.

Claim 38

The method of claim 32, wherein the transmitting step (d) includes the step of transmitting the activation signal to the coprocessor via a PCI bridge.

Claim 39

The method of claim 31, wherein the activating step includes the steps of: (g) storing activation state information in an internal control register of the coprocessor; and (h) storing program counter value in an internal program counter register of the coprocessor.

Claim 40

The method of claim 34, further comprising the step of setting an instruction trap flag in the coprocessor when the coprocessor encounters an instruction that cannot be processed.

Claim 41

The method of claim 34, further comprising the step of setting a task complete flag in the coprocessor when the coprocessor has completed a task.