US5923836A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Testing integrated circuit designs on a computer simulation using modified serialized scan patterns
Assignee: Texas Instruments Inc
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Filing: 1996-05-01
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Granted: 1999-07-13
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Expires: 2016-05-01
Abstract
Abstract A method to test an integrated circuit design on a computer simulation loads a desired simulation test vector in parallel into a scan chain (30). The simulation loads the desired vector at a slight offset or upstream shift allowing several serial shifts of the loaded vector through the scan chain (32). After the serial shifts, the initial IC state is set for executing an IC function (34). The IC function includes applying an input on the external pins and receiving an output from the external pins, given the initial IC state loaded by the simulation After executing the IC function, the simulation unloads the resulting IC state in parallel (36) and compares the resulting IC state to a target vector (38).
Inventors
- 👤 Phillip T. Barch
- 👤 Christopher J. Ellingham
- 👤 Frederick L. Wagner
- 👤 John R. Larkin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:47
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318558; G01R31/318563; G01R31/318544
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
134 words
A method to test an integrated circuit design on a computer simulation, comprising the steps of: generating a desired vector having state data to be loaded into a scan chain of the integrated circuit design; loading the scan chain with the state data of the desired vector in parallel to form a parallel scan chain of the integrated circuit design and the parallel scan chain with the state data being offset by a predetermined number of shifts; serially shifting the state data by the predetermined number of shifts along the scan chain to position the state data in the scan chain, to set a desired state of the integrated circuit design prior to executing a function of the integrated circuit design; and, executing said function of the integrated circuit design with the desired state.
Claim 2
Independent Claim
134 words
A method to test an integrated circuit design on a computer simulation, comprising the steps of: generating a desired vector having state data to be loaded into a scan chain of the integrated circuit design; loading the scan chain with the state data of the desired vector in parallel to form a parallel scan chain of the integrated circuit design and the parallel scan chain with the state data being offset by a predetermined number of shifts; serially shifting the state data by the predetermined number of shifts along the scan chain to position the state data in the scan chain, to set a desired state of the integrated circuit design prior to executing a function of the integrated circuit design; and, executing said function of the integrated circuit design with the desired state.
Claim 3
Dependent Claim
60 words
The method of claim 1, and further comprising the steps of: unloading in parallel a resulting state of the integrated circuit design from the execution, the resulting state of the integrated circuit design having the state data in the scan chain after executing the function; and comparing the resulting state of the integrated circuit design to a predetermined target vector.
Claim 4
Dependent Claim
68 words
The method of claim 1, and further comprising the steps of: shifting a resulting state of the integrated circuit design along the scan chain from the execution, the resulting state of the integrated circuit design having the state data in the scan chain after executing the function; unloading in parallel the resulting state; and comparing the resulting state of the integrated circuit design to a predetermined target vector.
Claim 5
Dependent Claim
21 words
The method of claim 1, wherein the step of shifting includes the step of validating the operation of the scan chain.
Claim 6
Dependent Claim
39 words
The method of claim 1, wherein the step of executing a function further comprises: applying an input vector to the integrated circuit design; and reading an output vector from the integrated circuit design after a predetermined amount of time.
Claim 7
Dependent Claim
30 words
The method of claim 1, wherein the step of generating a desired vector further including generating the desired vector from serialized scan patterns used in testing the fabricated integrated circuit.
Claim 8
Dependent Claim
65 words
The method of claim 1, wherein the step of generating a desired vector further comprises the steps of: generating a parallel test pattern on an automatic test pattern generator; generating, using the parallel test pattern, a serialized scan pattern for testing the fabricated integrated circuit; and generating, using the serialized scan pattern, the desired vector for testing the integrated circuit design on the computer simulation.
Claim 9
Independent Claim
146 words
A method to test an integrated circuit board design on a computer simulation, the integrated circuit board design comprising a plurality of integrated circuit components, comprising the steps of: generating a desired vector having state data to be loaded into a scan chain associated with the integrated circuit components; loading the scan chain with the state data of the desired vector in parallel to form a parallel scan chain and the parallel scan chain of the desired vector being offset by a predetermined number of shifts; serially shifting the state data the predetermined number of shifts along the parallel scan chain to position the state data in the scan chain, to set a desired state of the integrated circuit board design before execution of a function of the integrated circuit board design; and executing the function of the integrated circuit board design with the desired state.
Claim 10
Independent Claim
146 words
A method to test an integrated circuit board design on a computer simulation, the integrated circuit board design comprising a plurality of integrated circuit components, comprising the steps of: generating a desired vector having state data to be loaded into a scan chain associated with the integrated circuit components; loading the scan chain with the state data of the desired vector in parallel to form a parallel scan chain and the parallel scan chain of the desired vector being offset by a predetermined number of shifts; serially shifting the state data the predetermined number of shifts along the parallel scan chain to position the state data in the scan chain, to set a desired state of the integrated circuit board design before execution of a function of the integrated circuit board design; and executing the function of the integrated circuit board design with the desired state.
Claim 11
Dependent Claim
63 words
The method of claim 8, and further comprising the steps of: unloading in parallel a resulting state of the integrated circuit board design from the execution, the resulting state of the integrated circuit board design comprising the state data in the scan chain after executing the function; and comparing the resulting state of the integrated circuit board design to a predetermined target vector.
Claim 12
Dependent Claim
68 words
The method of claim 8, and further comprising the steps of: shifting a resulting state of the integrated circuit board design along the scan chain, the resulting state of the integrated circuit board design including the state data in the scan chain after executing the function; unloading in parallel the resulting state; and comparing the resulting state of the integrated circuit board design to a predetermined target vector.
Claim 13
Dependent Claim
21 words
The method of claim 8, wherein the step of shifting includes the step of validating the operation of the scan chain.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |