US5610826A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog signal monitor circuit and method
Assignee: Texas Instruments Inc
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Filing: 1994-05-13
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Granted: 1997-03-11
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Expires: 2014-05-13
Abstract
Abstract An analog signal monitoring (ASM) circuit (40, 42) non-intrusively monitors an analog circuit (20) within an electronic system. The ASM circuit (40,42) comprises input circuitry (80) that receives a plurality of analog signal inputs while the analog circuit (20) operates in a functional mode. Translation circuitry (142) associates with the input circuitry (80) for converting the analog signal inputs into digital signal representations of the analog signal inputs. Output circuitry (58) associates with the translation circuitry to output the digital representations. Control circuitry (114) controls the translation and output circuitry while the analog circuit (20) is in a functional mode. The ASM circuit (40, 42) also include an event qualification circuit (68) that includes input circuitry (236) to receive the digital signal representations, compare circuitry (104) to compare the received digital representations to an expected value and output a matched signal when a compared condition is identified.
Inventors
- 👤 Lee D. Whetsel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/316; G01R31/3163
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
161 words
An analog signal monitoring circuit for non-intrusively monitoring electronic circuitry including an analog circuit, comprising: input circuitry for receiving a plurality of analog signal inputs from the analog circuit; and test circuitry associated with said input circuitry for, while the electronic circuitry operates under timing control of a first clock, processing said analog signal inputs in response to predetermined conditions and synchronously with either one of said first clock and a second clock, said test circuitry including translation circuitry associated with said input circuitry for converting said analog signal inputs into digital signal representations of said analog signal inputs, output circuitry associated with said translation circuitry for outputting said digital signal representations, control circuitry for controlling said translation and said output circuitry to operate while said analog circuit is in a functioning mode, and event qualification circuitry connected to said output circuitry for indicating the occurrence of said predetermined conditions and controlling said test circuitry in response to said predetermined conditions.
Claim 2
Dependent Claim
161 words
An analog signal monitoring circuit for non-intrusively monitoring electronic circuitry including an analog circuit, comprising: input circuitry for receiving a plurality of analog signal inputs from the analog circuit; and test circuitry associated with said input circuitry for, while the electronic circuitry operates under timing control of a first clock, processing said analog signal inputs in response to predetermined conditions and synchronously with either one of said first clock and a second clock, said test circuitry including translation circuitry associated with said input circuitry for converting said analog signal inputs into digital signal representations of said analog signal inputs, output circuitry associated with said translation circuitry for outputting said digital signal representations, control circuitry for controlling said translation and said output circuitry to operate while said analog circuit is in a functioning mode, and event qualification circuitry connected to said output circuitry for indicating the occurrence of said predetermined conditions and controlling said test circuitry in response to said predetermined conditions.
Claim 3
Dependent Claim
20 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry comprises circuitry for storing said analog signal inputs.
Claim 4
Dependent Claim
20 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry comprises circuitry for compressing said digital signal representations.
Claim 5
Dependent Claim
22 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry comprises circuitry for storing and compressing said digital signal representations.
Claim 6
Dependent Claim
59 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry further comprises memory circuitry for storing said digital signal representations and wherein said output circuitry associates with said memory circuitry for outputting said stored digital signal representations and said control circuitry further controls said memory circuitry to operate while said analog circuit is in a functioning mode.
Claim 7
Dependent Claim
70 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry further comprises parallel signature analysis circuitry associated with said translation circuitry for compressing a plurality of said digital representations into a signature, wherein said output circuitry is associated with said parallel signature analysis circuitry to output said signature, and said control circuitry associates with said parallel signature analysis circuitry to control said compressing of said digital signal representations.
Claim 8
Dependent Claim
70 words
The analog signal monitoring circuit of claim 1, wherein said test circuits further comprises difference circuitry for measuring voltage differences between a plurality of received analog signal inputs, and wherein said translation circuitry associates with said difference circuitry to convert said voltage difference measurements into a plurality of digital signal representations, and said control circuitry further controls said difference circuitry to operate while said analog circuit is in functioning mode.
Claim 9
Dependent Claim
31 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry further comprises an expected data memory for storing a plurality of expected digital representations associated with said predetermined conditions.
Claim 10
Dependent Claim
45 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry is operable to compare expected digital signal representations with said digital signal representations received from the analog circuit and is operable to indicate whether said received representations match said expected digital signal representations.
Claim 11
Dependent Claim
28 words
The analog signal monitoring circuit of claim 1, further comprising circuitry for associating said analog signal monitoring circuit with an external test controller which provides said second clock.
Claim 12
Dependent Claim
30 words
The analog signal monitoring circuit of claim 1, further comprising circuitry associated with said event qualification circuitry for operating said analog signal monitoring circuit synchronous to said event qualification circuitry.
Claim 13
Dependent Claim
36 words
The analog signal monitoring circuit of claim 1, further comprising a plurality of test protocols associated with said event qualification circuitry for programmably actuating said event qualification circuitry in response to a plurality of matched signals.
Claim 14
Dependent Claim
33 words
The analog signal monitoring circuit of claim 12, wherein said test protocols comprise testing whether said analog signal inputs are at most a first expected value and at least a second expected value.
Claim 15
Dependent Claim
34 words
The analog signal monitoring circuit of claim 12, wherein said test protocols comprise testing whether said analog signal inputs are greater than a first expected value or, alternatively, less than a second expected value.
Claim 16
Dependent Claim
26 words
The analog signal monitoring circuit of claim 2, wherein said test protocols adjustably control the duration of test operations performed by said analog signal monitoring circuit.
Claim 17
Dependent Claim
26 words
The analog signal monitoring circuit of claim 1, further comprising a plurality of protocols for adjustably and programmably controlling the actuation of said event qualification circuitry.
Claim 18
Dependent Claim
15 words
The analog signal monitoring circuit of claim 1, packaged as a separate integrated circuit board.
Claim 19
Dependent Claim
25 words
The analog signal monitoring circuit of claim 1, mounted as an integrated circuit on a common substrate with at least one analog functional integrated circuit.
Claim 20
Dependent Claim
17 words
The analog signal monitoring circuit of claim 1, provided as a subcircuit within a larger integrated circuit.
Claim 21
Dependent Claim
48 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry is operable to compare expected digital signal representations with said digital signal representations received from said analog circuit and is operable to indicate whether said received representations have values no less than said expected digital representations.
Claim 22
Dependent Claim
48 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry is operable to compare expected digital signal representations with said digital signal representations received from said analog circuit and is operable to indicate whether said received representations are no greater than said expected digital signal representations.
Claim 23
Dependent Claim
47 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry is operable to compare expected digital signal representations with said digital signal representations received from said analog circuit and is operable to indicate whether said received representations are less than said expected digital signal representations.
Claim 24
Dependent Claim
47 words
The analog signal monitoring circuit of claim 1, wherein said test circuitry is operable to compare expected digital signal representations with said digital signal representations received from said analog circuit and is operable to indicate whether said received representations are greater than said expected digital signal representations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-10 | 2000-09-09 | 2001-03-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-10 | 2004-09-09 | 2005-03-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-10 | 2008-09-09 | 2009-03-11 | $7700.00 | Window Closed / Lapsed |