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US5923679A
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Error correction encoder, error correction decoder, and communication system
Assignee: Canon Inc
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Filing: 1996-10-15
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Granted: 1999-07-13
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Expires: 2016-10-15
Abstract
Abstract Error detection and correction capability is improved compared to the conventional art, without lowering the transmission efficiency. When a class dividing circuit 101 is supplied with the information code from a voice encoder, according to the definition assigned to the information code by the class divider extremely important class 0 information code is supplied to a CRC calculation circuit 102 and a block coding circuit 103, the next most important class 1 information code is supplied to a block coding circuit 105, and the next most important class 2 information code is supplied directly to an interleaving circuit 107. The CRC calculating circuit 102 obtains error correction information for the class 0 information code supplied from the class dividing circuit 101, generates data with error detection information appended thereto, and supplies it to a class 0 block coding circuit 103. The class 0 block coding circuit 103 carries out block coding from the data having error detection information appended and class 0 data.
Inventors
- 👤 Katsutoshi Itoh
- 👤 Kenichiro Hosoda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:02
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/35; H04; H04L; H04L1/00; H04L2001/0098
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
69 words
An error correction encoder, comprising: a calculating circuit to calculate and generate error detection information having a specified bit length, based on an input data string; and error correction encoding means to form plural data blocks from bits of the input data string and bits of the error detection information, to apply error correction code to each of the plural data blocks, and to generate error correction encoded data.
Claim 2
Dependent Claim
69 words
An error correction encoder, comprising: a calculating circuit to calculate and generate error detection information having a specified bit length, based on an input data string; and error correction encoding means to form plural data blocks from bits of the input data string and bits of the error detection information, to apply error correction code to each of the plural data blocks, and to generate error correction encoded data.
Claim 3
Dependent Claim
29 words
The error correction encoder claimed in claim 1, wherein each of the plural data blocks includes bits of the input data string and bits of the error detection information.
Claim 4
Dependent Claim
24 words
The error correction encoder claimed in claim 1, wherein one of the plural data blocks includes all the bits of the error detection information.
Claim 5
Dependent Claim
163 words
An error correction encoder, comprising: input information classification means for classifying different categories of input information into a plurality of classifications according to a degree of importance of the category of input information, and for separately generating most important information and second-most important information; a calculating circuit to calculate and generate error detection information having a specified bit length based on the most important information; first error correction encoding means to form plural first data blocks having a specified bit length, using bits of the most important information and bits of the error detection information, to apply first error correction code to each of the plural first data blocks, and to generate first error correction encoded data; and second error correction encoding means to form plural second data blocks having a specified bit length using bits of the second-most important information, to apply second error correction code to each of the plural second data. blocks, and to generate second error correction encoded data.
Claim 6
Dependent Claim
163 words
An error correction encoder, comprising: input information classification means for classifying different categories of input information into a plurality of classifications according to a degree of importance of the category of input information, and for separately generating most important information and second-most important information; a calculating circuit to calculate and generate error detection information having a specified bit length based on the most important information; first error correction encoding means to form plural first data blocks having a specified bit length, using bits of the most important information and bits of the error detection information, to apply first error correction code to each of the plural first data blocks, and to generate first error correction encoded data; and second error correction encoding means to form plural second data blocks having a specified bit length using bits of the second-most important information, to apply second error correction code to each of the plural second data. blocks, and to generate second error correction encoded data.
Claim 7
Dependent Claim
33 words
The error correction encoder claimed in claim 4, further comprising: interleave means to interleave the first error correction encoded data and the second error correction encoded data, and to generate an interleaved result.
Claim 8
Dependent Claim
32 words
The error correction encoder claimed in claim 4, wherein: the input information classification means classifies one of voice path coefficients and power information of the input information as the most important information.
Claim 9
Dependent Claim
30 words
The error correction encoder claimed in claim 4, wherein the first error correction encoding means further uses bits of the second-most important information to form the plural first data blocks.
Claim 10
Dependent Claim
20 words
The error correction encoder claimed in claim 4, wherein the input information classification means further separately generates least important information.
Claim 11
Dependent Claim
37 words
The error correction encoder claimed in claim 8, further comprising: interleave means to interleave the first error correction encoded data, the second error correction encoded data, and the least important information, and to generate an interleaved result.
Claim 12
Dependent Claim
30 words
The error correction encoder claimed in claim 4, wherein the second error correction encoding means forms the plural second data blocks using only the bits of the second-most important information.
Claim 13
Dependent Claim
197 words
A communication system comprising an error correction encoder and an error correction decoder, wherein: the error correction encoder comprises: a calculating circuit to calculate and generate error detection information having a specified bit length based on an input data string; and error correction encoding means to form plural data blocks from bits of the input data string and bits of the error detection information, to apply error correction code to each of the plural data blocks, and to generate plural groupings of error correction encoded data; and the error correction decoder comprises: decode candidate estimating means for carrying out error correction decoding processing for each of said plural groupings of error correction encoded data, and estimating at least two decode data candidates for each of the plural groupings of error correction encoded data; and valid decode candidate determining means for combining the decode data candidates for each of the plural groupings of error correction encoded data to form plural combinations of decode data candidates, determining whether each combination of decode data candidates has an error, and designating any combination of decode data candidates that has no error as being valid data corresponding to the input data string.
Claim 14
Dependent Claim
197 words
A communication system comprising an error correction encoder and an error correction decoder, wherein: the error correction encoder comprises: a calculating circuit to calculate and generate error detection information having a specified bit length based on an input data string; and error correction encoding means to form plural data blocks from bits of the input data string and bits of the error detection information, to apply error correction code to each of the plural data blocks, and to generate plural groupings of error correction encoded data; and the error correction decoder comprises: decode candidate estimating means for carrying out error correction decoding processing for each of said plural groupings of error correction encoded data, and estimating at least two decode data candidates for each of the plural groupings of error correction encoded data; and valid decode candidate determining means for combining the decode data candidates for each of the plural groupings of error correction encoded data to form plural combinations of decode data candidates, determining whether each combination of decode data candidates has an error, and designating any combination of decode data candidates that has no error as being valid data corresponding to the input data string.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |