US5923200A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Phase modulator circuit
Assignee: Sony Corp
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Filing: 1995-09-22
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Granted: 1999-07-13
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Expires: 2015-09-22
Abstract
Abstract An input signal and a signal obtained by delaying that input signal are compared, an output signal is produced based on the amount of the delay, and the output signal is used to form a control signal by a low pass filter. The delay of the input signal is controlled so as to produce a plurality of stable clocks and enable stable high speed signal processing without raising the clock frequency.
Inventors
- 👤 Kazutoshi Shimizume
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:36
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/00019; H03K2005/00026
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
281 words
A phase modulator circuit, comprising: a phase comparator for detecting a phase difference between a first signal and a reference clock signal and outputting a signal in accordance with said detection, a delay control signal producing circuit for receiving said output signal of the phase comparator and producing a delay control signal in accordance with a voltage level of said phase comparator output signal, and a variable phase shifter for receiving said delay control signal, delaying said reference clock signal by an amount of delay in accordance with said delay control signal to generate said first signal, wherein said variable phase shifter comprises a plurality of cells each of which delays said reference clock signal by a predetermined amount, wherein each of said cells comprises three inverters connected in cascade, wherein each of said inverters comprises a P-channel MOS transistor and an N-channel MOS transistor connected in series between a first power source and a second power source, wherein said delay control signal is supplied to a gate of the P-channel MOS transistor of a first of said three inverters of a first of said unit cells and said reference clock signal is supplied to a gate of the N-channel MOS transistor of the first of said three inverters of said first of said unit cells, and wherein said modulator circuit further comprises a capacitor having a first terminal connected to ground and a second terminal connected to a drain of said P-channel MOS transistor of said first of said three inverters of said first of said unit cells and a source of said N-channel MOS transistor of said first of said three inverters of said first of said unit cells.
Claim 2
Dependent Claim
281 words
A phase modulator circuit, comprising: a phase comparator for detecting a phase difference between a first signal and a reference clock signal and outputting a signal in accordance with said detection, a delay control signal producing circuit for receiving said output signal of the phase comparator and producing a delay control signal in accordance with a voltage level of said phase comparator output signal, and a variable phase shifter for receiving said delay control signal, delaying said reference clock signal by an amount of delay in accordance with said delay control signal to generate said first signal, wherein said variable phase shifter comprises a plurality of cells each of which delays said reference clock signal by a predetermined amount, wherein each of said cells comprises three inverters connected in cascade, wherein each of said inverters comprises a P-channel MOS transistor and an N-channel MOS transistor connected in series between a first power source and a second power source, wherein said delay control signal is supplied to a gate of the P-channel MOS transistor of a first of said three inverters of a first of said unit cells and said reference clock signal is supplied to a gate of the N-channel MOS transistor of the first of said three inverters of said first of said unit cells, and wherein said modulator circuit further comprises a capacitor having a first terminal connected to ground and a second terminal connected to a drain of said P-channel MOS transistor of said first of said three inverters of said first of said unit cells and a source of said N-channel MOS transistor of said first of said three inverters of said first of said unit cells.
Claim 3
Dependent Claim
226 words
A signal processing circuit comprising: a plurality of registers connected in cascade, wherein each of said plurality of registers is supplied with a first clock signal and supplied with an input digital signal; an operation processing circuit having an input terminal which receives signals from an input terminal and an output terminal of a final stage of said plurality of registers; and a second register supplied with an output signal from said operation processing circuit and a second clock signal; wherein said first and second clock signals are formed by phase modulation from a single reference clock signal; wherein said phase modulation is performed by a phase modulator circuit comprising: a phase comparator for detecting a phase difference between a first signal and said reference clock signal and outputting a signal in accordance with said detection, a delay control signal producing circuit for receiving said output signal of the phase comparator and producing a delay control signal in accordance with a voltage level of said phase comparator output signal, and a variable phase shifter for receiving the delay control signal, delaying the reference clock signal by an amount of delay in accordance with said delay control signal to generate said first signal; wherein said variable phase shifter is formed by a plurality of cells each of which delays said reference clock signal by a predetermined amount.
Claim 4
Dependent Claim
226 words
A signal processing circuit comprising: a plurality of registers connected in cascade, wherein each of said plurality of registers is supplied with a first clock signal and supplied with an input digital signal; an operation processing circuit having an input terminal which receives signals from an input terminal and an output terminal of a final stage of said plurality of registers; and a second register supplied with an output signal from said operation processing circuit and a second clock signal; wherein said first and second clock signals are formed by phase modulation from a single reference clock signal; wherein said phase modulation is performed by a phase modulator circuit comprising: a phase comparator for detecting a phase difference between a first signal and said reference clock signal and outputting a signal in accordance with said detection, a delay control signal producing circuit for receiving said output signal of the phase comparator and producing a delay control signal in accordance with a voltage level of said phase comparator output signal, and a variable phase shifter for receiving the delay control signal, delaying the reference clock signal by an amount of delay in accordance with said delay control signal to generate said first signal; wherein said variable phase shifter is formed by a plurality of cells each of which delays said reference clock signal by a predetermined amount.
Claim 5
Dependent Claim
230 words
A signal processing circuit comprising: a plurality of registers connected in cascade, wherein each of said plurality of registers is supplied with a first clock signal and supplied with an input digital signal; an operation processing circuit having an input terminal which receives signals from an input terminal and an output terminal of a final stage of said plurality of registers; and a second register supplied with an output signal from said operation processing circuit and a second clock signal; wherein said first and second clock signals are formed by phase modulation from a single reference clock signal; wherein said phase modulation is performed by a phase modulator circuit comprising: a phase comparator for detecting a phase difference between a first signal and said reference clock signal and outputting a signal in accordance with said detection, a delay control signal producing circuit for receiving said output signal of the phase comparator and producing a delay control signal in accordance with a voltage level of said phase comparator output signal, and a variable phase shifter for receiving the delay control signal, delaying the reference clock signal by an amount of delay in accordance with said delay control signal to generate said first signal; wherein said variable phase shifter comprises a cascade connection of a plurality of unit cells comprising inverters for adjusting an amount of delay of said reference clock signal.
Claim 6
Dependent Claim
230 words
A signal processing circuit comprising: a plurality of registers connected in cascade, wherein each of said plurality of registers is supplied with a first clock signal and supplied with an input digital signal; an operation processing circuit having an input terminal which receives signals from an input terminal and an output terminal of a final stage of said plurality of registers; and a second register supplied with an output signal from said operation processing circuit and a second clock signal; wherein said first and second clock signals are formed by phase modulation from a single reference clock signal; wherein said phase modulation is performed by a phase modulator circuit comprising: a phase comparator for detecting a phase difference between a first signal and said reference clock signal and outputting a signal in accordance with said detection, a delay control signal producing circuit for receiving said output signal of the phase comparator and producing a delay control signal in accordance with a voltage level of said phase comparator output signal, and a variable phase shifter for receiving the delay control signal, delaying the reference clock signal by an amount of delay in accordance with said delay control signal to generate said first signal; wherein said variable phase shifter comprises a cascade connection of a plurality of unit cells comprising inverters for adjusting an amount of delay of said reference clock signal.
Claim 7
Dependent Claim
47 words
A signal processing circuit as set forth in claim 3, wherein said unit cells each comprise cascade connections of at least three inverters constituted by a P-channel MOS transistor and an N-channel MOS transistor connected in series between a first power source and a second power source.
Claim 8
Dependent Claim
68 words
A signal processing circuit as set forth in claim 4, wherein said delay control signal is supplied to a gate of the P-channel MOS transistor of a first of said three inverters of a first of said unit cells and said reference clock signal is supplied to a gate of the N-channel MOS transistor of the first of said three inverters of said first of said unit cells.
Claim 9
Dependent Claim
46 words
A phase modulator circuit as set forth in claim 1, wherein said second terminal of said capacitor is connected to gates of the P-channel MOS transistor and the N-channel MOS transistor of a second inverter of said three inverters of said first of said unit cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-12 | 2003-01-11 | 2003-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-12 | 2007-01-11 | 2007-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-12 | 2011-01-11 | 2011-07-13 | $7700.00 | Window Closed / Lapsed |