Abstract A memory having a read function for generating a plurality of data bits on a single output pin includes a control circuit, a sense amplifier circuit, and a decoder. The control circuit generates a decoder control pulse responding to the control pulse generated from an address transition detector receiving a first address. The sense amplifier circuit senses data bits from a memory array of the memory and is coupled to the output pin through a data output buffer. The decoder receives a second address and provides decoding signals to the sense amplifier circuitry in response to the control pulse generated from the control circuit. The read-out operation according to the invention is performed sufficiently and stably even when a propagation skew occurs between the first address and the second address.
A semiconductor memory having a read function that generates a plurality of data bits to a single output pin, the memory comprising: a memory array for storing the plurality of data bits; an address transition detector for generating a precharge control pulse responding to a transition of a first address; a control circuit for generating a decoder control pulse in response to the precharge control pulse; a sense amplifier circuit for reading some of the plurality of data bits from the memory array, the sense amplifier circuit comprising data latches and transmission circuits, and being coupled to an output pin through a data output buffer; and a decoder for receiving a second address and for providing decoding signals to the sense amplifier circuit in response to the decoder control pulse.
Claim 2
Dependent Claim
130 words
A semiconductor memory having a read function that generates a plurality of data bits to a single output pin, the memory comprising: a memory array for storing the plurality of data bits; an address transition detector for generating a precharge control pulse responding to a transition of a first address; a control circuit for generating a decoder control pulse in response to the precharge control pulse; a sense amplifier circuit for reading some of the plurality of data bits from the memory array, the sense amplifier circuit comprising data latches and transmission circuits, and being coupled to an output pin through a data output buffer; and a decoder for receiving a second address and for providing decoding signals to the sense amplifier circuit in response to the decoder control pulse.
Claim 3
Dependent Claim
34 words
A semiconductor memory as recited in claim 1, wherein the number of the sense amplifiers, the data latches, and transmission circuits in the sense amplifier circuit is equal to the number of data bits.
Claim 4
Dependent Claim
27 words
A semiconductor memory as recited in claim 1, wherein the number of decoding signals provided by the decoder is being equal to the number of data bits.