US5920503A
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US
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Flash memory with novel bitline decoder and sourceline latch
Assignee: Secure Axcess LLC
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Filing: 1997-05-02
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Granted: 1999-07-06
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Expires: 2017-05-02
Abstract
Abstract A flash memory with a novel bitline and sourceline decoder includes a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline. A second bank of flash transistors forms a plurality of rows and a plurality of columns, and has wordlines, bitlines and a second sourceline. A wordline decoder is coupled to the wordlines and configured to receive a wordline address signal and to decode the wordline address signal to select a wordline. A bitline and sourceline decoder is coupled to the bitlines and sourcelines and configured to receive a bitline address signal and to decode the bitline address signal to select predetermined bitlines and sourcelines. The bitline and sourceline decoder includes a latch coupled to the bitlines, the first sourceline and the second sourceline and configured to latch selected bitlines and sourcelines to selectively provide erase voltages on the selected bitlines and sourcelines. As a result of the novel memory architecture, a flexible number of bytes can be selected for erasure. The selected number of bytes can range from one byte to 64K bytes or more. Advantages of the invention include reduced erase/write cycle time and an improved expected lifetime of the flash memory due to reduced stress on the flash transistors within the flash memory.
Inventors
- 👤 Peter W. Lee
- 👤 Fu-Chang Hsu
- 👤 Hsing-Ya Tsao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:42
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3427; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5635; G11C11/5642; G11C16/08; G11C16/10; G11C16/14; G11C16/16; G11C16/3404; G11C16/3409; G11C16/3431; G11C2211/00; G11C2211/56; G11C2211/564; G11C2211/5642; G11C2216/00; G11C2216/12; G11C2216/20; G11C8/00
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
144 words
A flash memory comprising: a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline; a second bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a second sourceline; a wordline decoder coupled to said wordlines and configured to receive a wordline address signal and to decode said wordline address signal to select a wordline; and a bitline and sourceline decoder coupled to said bitlines, said first sourceline and said second sourceline and configured to receive a bitline address signal and to decode said bitline address signal to select predetermined bitlines and at least one sourceline, said bitline and sourceline decoder including a latch configured to latch a selected sourceline to selectively provide a sourceline erase voltage on said selected sourceline.
Claim 2
Dependent Claim
144 words
A flash memory comprising: a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline; a second bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a second sourceline; a wordline decoder coupled to said wordlines and configured to receive a wordline address signal and to decode said wordline address signal to select a wordline; and a bitline and sourceline decoder coupled to said bitlines, said first sourceline and said second sourceline and configured to receive a bitline address signal and to decode said bitline address signal to select predetermined bitlines and at least one sourceline, said bitline and sourceline decoder including a latch configured to latch a selected sourceline to selectively provide a sourceline erase voltage on said selected sourceline.
Claim 3
Dependent Claim
66 words
The flash memory of claim 1, wherein: said wordline decoder is configured to provide a wordline erase voltage on a selected wordline in response to an erase signal, said bitline and sourceline decoder is configured to float selected bitlines in response to said erase signal, and said latch is configured to sustain said sourceline erase voltage on said selected sourceline in response to said erase signal.
Claim 4
Dependent Claim
19 words
The flash memory of claim 2, wherein: said latch is configured to reset in response to a read signal.
Claim 5
Dependent Claim
67 words
The flash memory of claim 2, wherein: said wordline decoder is configured to provide a wordline erase voltage on all wordlines in response to an erase all signal, said bitline and sourceline decoder is configured to float all bitlines in response to said erase all signal, and said latch is configured to provide said sourceline erase voltage on all sourcelines in response to said erase all signal.
Claim 6
Dependent Claim
33 words
The flash memory of claim 2, wherein: said latch is configured to reset in response to a read signal, and said wordline latch is configured to reset in response to a read signal.
Claim 7
Dependent Claim
33 words
The flash memory of claim 1, further comprising: a scan circuit coupled to said bitline and sourceline decoder and configured to selectively scan through said latch to determine the state of said latch.
Claim 8
Dependent Claim
33 words
The flash memory of claim 1, further comprising: a wordline latch coupled to said wordlines and configured to latch a selected wordline to selectively provide a wordline erase voltage on said selected wordline.
Claim 9
Dependent Claim
66 words
The flash memory of claim 7, wherein: said wordline latch is configured to provide a wordline erase voltage on said selected wordline in response to an erase signal, said bitline and sourceline decoder is configured to float selected bitlines in response to said erase signal, and said latch is configured to provide said sourceline erase voltage on said selected sourceline in response to said erase signal.
Claim 10
Dependent Claim
68 words
The flash memory of claim 8, wherein: said wordline latch is configured to provide a wordline erase voltage on all wordlines in response to an erase all signal, said bitline and sourceline decoder is configured to selectively float all bitlines in response to said erase all signal, and said latch is configured to provide said sourceline erase voltage on all sourcelines in response to said erase all signal.
Claim 11
Independent Claim
131 words
A method of performing a procedure in a flash memory having a first bank of flash transistors with a first sourceline, and a second bank of flash transistors with a second sourceline, said method comprising the steps of: receiving an address of a word requested to be erased; decoding said address to identify a word in one of said first bank and said second bank; latching a sourceline corresponding to said identified word in one of said first bank and said second bank; and in response to an erase signal, performing the steps of: (a) providing a wordline erase voltage to gates of transistors for said identified word; (b) floating bitlines to drains of said transistors for said identified word; and (c) providing a sourceline erase voltage to said latched sourceline.
Claim 12
Independent Claim
131 words
A method of performing a procedure in a flash memory having a first bank of flash transistors with a first sourceline, and a second bank of flash transistors with a second sourceline, said method comprising the steps of: receiving an address of a word requested to be erased; decoding said address to identify a word in one of said first bank and said second bank; latching a sourceline corresponding to said identified word in one of said first bank and said second bank; and in response to an erase signal, performing the steps of: (a) providing a wordline erase voltage to gates of transistors for said identified word; (b) floating bitlines to drains of said transistors for said identified word; and (c) providing a sourceline erase voltage to said latched sourceline.
Claim 13
Dependent Claim
20 words
The method of claim 10, further comprising the step of: in response to a read signal, resetting said latched sourceline.
Claim 14
Dependent Claim
50 words
The method of claim 10, further comprising the step of: in response to an erase all signal, performing the steps of: (a) providing a wordline erase voltage to gates of all transistors; (b) floating bitlines to drains of all transistors; and (c) providing a sourceline erase voltage to all sourcelines.
Claim 15
Dependent Claim
21 words
The method of claim 10, further comprising the step of: selectively scanning the latch to determine the state of the latch.
Claim 16
Dependent Claim
131 words
The method of claim 10 where said flash memory further has a third bank of flash transistors with a third sourceline, said method further comprising the steps of: receiving a second address of a second word requested to be erased; decoding said second address to identify a second word in one of said second bank and said third bank; latching a second sourceline corresponding to said second identified word in one of said second bank and said third bank; and in response t o said erase signal, performing the steps of: (a) providing a wordline erase voltage to gates of transistors for said second identified word; (b) floating bitlines to drains of said transistors for said second identified word; and (c) providing a sourceline erase voltage to said second latched sourceline.
Claim 17
Dependent Claim
49 words
The method of claim 14, further comprising the steps of: latching a wordline corresponding to said identified word in one of said first bank and said second bank; and latching a second wordline corresponding to said second identified word in one of said second bank and said third bank.
Claim 18
Dependent Claim
25 words
The method of claim 15, further comprising the step of: in response to a read signal, resetting said latched sourcelines and resetting said latched wordlines.
Claim 19
Dependent Claim
21 words
The method of claim 14, further comprising the step of: selectively scanning the latch to determine the state of the latch.
Claim 20
Dependent Claim
179 words
A flash memory comprising: a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline; a second bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a second sourceline; a wordline decoder coupled to said wordlines and configured to receive a wordline address signal and to decode said wordline address signal to select a wordline; a bitline and sourceline decoder configured to receive a bitline address signal and to decode said bitline address signal and to assert at least one of a plurality of bitline and sourceline select lines, said bitline and sourceline decoder including a latch configured to selectively latch at least one of said bitline and sourceline select lines; and a Y selector coupled to said bitline and sourceline select lines, said bitlines, said first sourceline and said second sourceline and configured to receive a signal on each of said bitline and sourceline select lines to select predetermined bitlines and at least one sourceline.
Claim 21
Dependent Claim
179 words
A flash memory comprising: a first bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a first sourceline; a second bank of flash transistors forming a plurality of rows and a plurality of columns, and having wordlines, bitlines and a second sourceline; a wordline decoder coupled to said wordlines and configured to receive a wordline address signal and to decode said wordline address signal to select a wordline; a bitline and sourceline decoder configured to receive a bitline address signal and to decode said bitline address signal and to assert at least one of a plurality of bitline and sourceline select lines, said bitline and sourceline decoder including a latch configured to selectively latch at least one of said bitline and sourceline select lines; and a Y selector coupled to said bitline and sourceline select lines, said bitlines, said first sourceline and said second sourceline and configured to receive a signal on each of said bitline and sourceline select lines to select predetermined bitlines and at least one sourceline.
Claim 22
Dependent Claim
33 words
The flash memory of claim 18, further comprising: a scan circuit coupled to said bitline and sourceline decoder and configured to selectively scan through said latch to determine the state of said latch.
Claim 23
Dependent Claim
33 words
The flash memory of claim 18, further comprising: a wordline latch coupled to said wordlines and configured to latch a selected wordline to selectively provide a wordline erase voltage on said selected wordline.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-05 | 2003-01-04 | 2003-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-05 | 2007-01-04 | 2007-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-05 | 2011-01-04 | 2011-07-06 | $7700.00 | Window Closed / Lapsed |