Method of manufacturing semiconductor device having multilayer wiring structure, with improved version of step of forming interlayer dielectric layer

Claim 1

A method of manufacturing a semiconductor device having a multilayered wiring structure, comprising the steps of: forming a first wiring portion on a semiconductor substrate; introducing H 2 O 2 and an aromatic or heterocyclic compound containing an Si--H group into a reaction chamber in which a semiconductor device is contained, and making them react with each other in a vacuum atmosphere of 665 Pa or lower at a temperature in a range of -10° C. to +10° C., thereby obtaining an intermediate reaction product on said semiconductor substrate and said first wiring portion, the intermediate reaction product having a planarization property in which a reflow thereof is promoted due to the Si--H group; forming an interlayer insulation film by subjecting said intermediate reaction product to a heat treatment so as to induce a dehydration reaction, thereby obtaining a silicon-based oxide film serving as said interlayer insulation film having a reflow shape, a network structure and a low dielectric constant; forming a plasma CVD SiO 2 film on said interlayer insulation film; forming a contact hole in said interlayer insulation film and said plasma CVD SiO 2 film which communicates to said first wiring portion; and forming a second wiring portion which communicates to said first wiring portion via said interlayer insulation film, said plasma CVD SiO 2 film and said contact hole.

Claim 2

A method of manufacturing a semiconductor device having a multilayered wiring structure, comprising the steps of: forming a first wiring portion on a semiconductor substrate; introducing H 2 O 2 and an aromatic or heterocyclic compound containing an Si--H group into a reaction chamber in which a semiconductor device is contained, and making them react with each other in a vacuum atmosphere of 665 Pa or lower at a temperature in a range of -10° C. to +10° C., thereby obtaining an intermediate reaction product on said semiconductor substrate and said first wiring portion, the intermediate reaction product having a planarization property in which a reflow thereof is promoted due to the Si--H group; forming an interlayer insulation film by subjecting said intermediate reaction product to a heat treatment so as to induce a dehydration reaction, thereby obtaining a silicon-based oxide film serving as said interlayer insulation film having a reflow shape, a network structure and a low dielectric constant; forming a plasma CVD SiO 2 film on said interlayer insulation film; forming a contact hole in said interlayer insulation film and said plasma CVD SiO 2 film which communicates to said first wiring portion; and forming a second wiring portion which communicates to said first wiring portion via said interlayer insulation film, said plasma CVD SiO 2 film and said contact hole.

Claim 3

A method of manufacturing a semiconductor device having a multilayered wiring structure, comprising the steps of: forming a first wiring portion on a semiconductor substrate; applying an aromatic or heterocyclic compound containing an Si--H group on said first wiring portion and said semiconductor substrate by a spin-coat technique; forming an interlayer insulation film having a network structure by carrying out a heat treatment so that a dehydration reaction takes place in said applied compound; forming a plasma CVD SiO 2 film on said interlayer insulation film; forming a contact hole in said interlayer insulation film and said plasma CVD SiO 2 film which communicates to said first wiring portion; and forming a second wiring portion which communicates to said first wiring portion via said interlayer insulation film, said plasma CVD SiO 2 film and said contact hole.

Claim 4

A method of manufacturing a semiconductor device having a multilayered wiring structure, comprising the steps of: forming a first wiring portion on a semiconductor substrate; applying an aromatic or heterocyclic compound containing an Si--H group on said first wiring portion and said semiconductor substrate by a spin-coat technique; forming an interlayer insulation film having a network structure by carrying out a heat treatment so that a dehydration reaction takes place in said applied compound; forming a plasma CVD SiO 2 film on said interlayer insulation film; forming a contact hole in said interlayer insulation film and said plasma CVD SiO 2 film which communicates to said first wiring portion; and forming a second wiring portion which communicates to said first wiring portion via said interlayer insulation film, said plasma CVD SiO 2 film and said contact hole.