Patent US5915203A successfully refreshed from Google Patents.
US5915203A
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US
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Method for producing deep submicron interconnect vias
Assignee: Philips Semiconductors Inc
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Filing: 1997-06-10
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Granted: 1999-06-22
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Expires: 2017-06-10
Abstract
Abstract A method of producing deep submicron vias is described in which a metal blanket layer is formed on a premetal dielectric and patterned to form line elements. An intermetal dielectric is then deposited over the patterned metal and chemically mechanically polished down to the top of the line elements. A second metal blanket layer is then deposited and patterned to form via studs. An intermetal dielectric is also deposited over the patterned metal via studs and polished down to the tops of the studs. The process is repeated until a multilevel integrated circuit is formed.
Inventors
- 👤 Samit Sengupta
- 👤 Subhas Bothra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 20:17
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/42; H10W20/01; H10W20/031; H10W20/063; H10W20/0633; H10W20/071; H10W20/092
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
213 words
A method of forming interconnect vias in a semiconductor device comprising, in sequence, the steps of: depositing a first layer of metal on a substrate, said first layer of metal including an anti-reflective layer on its top surface; forming a first metal pattern in said first metal layer; depositing a first layer of dielectric over said first metal pattern and said substrate to a level above said first metal pattern to a sufficient thickness to allow subsequent polishing down to the top level of said first metal pattern; polishing said first layer of dielectric down to the top level of said first metal pattern; depositing a second layer of metal directly onto the polished surface of said first metal pattern and said dielectric, said second layer of metal including an anti-reflective layer on its top surface; etching said second layer of metal in a second pattern leaving metal stubs in locations where interconnects are desired; depositing a second layer of dielectric over said stubs and the exposed portions of said first metal pattern and said first layer of dielectric; polishing said second layer of dielectric at least down to the top level of said stubs; and depositing a third layer of metal over the polished surface of said second pattern and said dielectric.
Claim 2
Independent Claim
213 words
A method of forming interconnect vias in a semiconductor device comprising, in sequence, the steps of: depositing a first layer of metal on a substrate, said first layer of metal including an anti-reflective layer on its top surface; forming a first metal pattern in said first metal layer; depositing a first layer of dielectric over said first metal pattern and said substrate to a level above said first metal pattern to a sufficient thickness to allow subsequent polishing down to the top level of said first metal pattern; polishing said first layer of dielectric down to the top level of said first metal pattern; depositing a second layer of metal directly onto the polished surface of said first metal pattern and said dielectric, said second layer of metal including an anti-reflective layer on its top surface; etching said second layer of metal in a second pattern leaving metal stubs in locations where interconnects are desired; depositing a second layer of dielectric over said stubs and the exposed portions of said first metal pattern and said first layer of dielectric; polishing said second layer of dielectric at least down to the top level of said stubs; and depositing a third layer of metal over the polished surface of said second pattern and said dielectric.
Claim 3
Dependent Claim
27 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said first layer of dielectric is a high density plasma oxide.
Claim 4
Dependent Claim
29 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said step of polishing said first layer of dielectric comprises chemical mechanical polishing.
Claim 5
Dependent Claim
29 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 together with the additional step of sputter etching said polished first layer of dielectric.
Claim 6
Dependent Claim
21 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said second layer is aluminum.
Claim 7
Dependent Claim
21 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said anti-reflective layer is TiN.
Claim 8
Dependent Claim
21 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said anti-reflective layer is TiW.
Claim 9
Dependent Claim
27 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said second layer of dielectric is a high density plasma oxide.
Claim 10
Dependent Claim
29 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said step of polishing said second layer of dielectric comprises chemical mechanical polishing.
Claim 11
Dependent Claim
33 words
A method of forming interconnect vias in a semiconductor device as defined in claim 1 wherein said first layer of metal and said second layer of metal are formed of the same metal.
Claim 12
Dependent Claim
21 words
A method of forming interconnect vias in a semiconductor device as defined in claim 10 wherein said same metal is aluminum.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-21 | 2010-12-21 | 2011-06-22 | $7700.00 | Window Closed / Lapsed |