Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at an active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at a first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at a second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at the second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder.

Claim 3

A circuit according to claim 1, wherein said signal level fixing circuit is a circuit for fixing all of the plurality of bits of the first signal at a predetermined level.

Claim 4

A circuit according to claim 1, wherein said internal circuit is a memory cell array which has a plurality of word lines and a plurality of bit lines, accesses an address corresponding to a selected word line and a selected bit line among said plurality of word lines and said plurality of bit lines in the ordinary operation mode, and stops access in the standby mode to set a memory content holding state, and said decoder is at least a row decoder of a row decoder for receiving the first signal as an address signal, decoding the first supplied bit of the first signal, setting one of said plurality of word lines at active level, and selecting said active-level word line, and a column decoder for decoding a supplied second bit of the first signal and selecting a predetermined bit line of said plurality of bit lines.

Claim 5

A circuit according to claim 1, wherein said internal circuit is a circuit including a selector for selecting one of a plurality of third signals in accordance with a selection signal, and an internal processing unit for, in the ordinary operation mode, performing a predetermined processing operation in response to the third signal selected by said selector and, in the standby mode, stopping the predetermined processing operation to be set in a low power consumption state, and said decoder is a circuit for decoding the first signal supplied thereto and outputting the selection signal.

Claim 6

A circuit according to claim 1, further comprising an output level control circuit for in the standby mode, setting a bit of the second signal, which is supplied from said decoder and set at active level, at inactive level, and supplying the inactive-level bit to said internal circuit.

Claim 7

A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at an active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at a first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at a second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at the second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder, wherein said internal circuit is a circuit including a selector for selecting one of a plurality of third signals in accordance with a selection signal, and an internal processing unit for, in the ordinary operation mode, performing a predetermined processing operating in response to the third signal selected by said selector and, in the standby mode, stopping the predetermined processing operating to be set in a low power consumption state, and said decoder is a circuit for decoding the first signal supplied thereto and out putting the selection signal.

Claim 8

A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at an active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at a first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at a second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at the second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder, wherein said internal circuit is a circuit including a selector for selecting one of a plurality of third signals in accordance with a selection signal, and an internal processing unit for, in the ordinary operation mode, performing a predetermined processing operating in response to the third signal selected by said selector and, in the standby mode, stopping the predetermined processing operating to be set in a low power consumption state, and said decoder is a circuit for decoding the first signal supplied thereto and out putting the selection signal.

Claim 9

A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at an active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at a first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at a second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at the second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder, wherein during each standby mode said decoder sets the same wordline active.

Claim 10

A semiconductor integrated circuit having a decoder for decoding a first signal supplied thereto and having a plurality of bits and outputting a second signal in which only a predetermined bit of the plurality of bits of the first signal is set at an active level, and an internal circuit for, in an ordinary operation mode in which a standby signal is at a first level, performing a predetermined processing operation in response to the second signal decoded by said decoder and, in a standby mode in which the standby signal is at a second level, stopping the predetermined processing operation to be set in a low power consumption state, comprising a signal level fixing circuit for, when the standby signal is at the second level, fixing the predetermined bit of the plurality of bits of the first signal at predetermined level, and supplying a resultant signal to said decoder, wherein during each standby mode said decoder sets the same wordline active.

Claim 11

The circuit of claim 7, wherein said signal level fixing circuit comprises an OR gate for each of the plurality of bits of the first signal, each said OR gate comprising a standby mode input wherein the output of each OR gate is set to an active level during the standby mode so that all inputs to said decoder are supplied with all active values during standby mode.