Patent US5914903A successfully refreshed from Google Patents.
US5914903A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Monterey Research LLC
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Filing: 1998-01-30
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Granted: 1999-06-22
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Expires: 2018-01-30
Abstract
Abstract A semiconductor memory device includes a plurality of cell blocks each having a plurality of memory cells, a plurality of bit lines for reading data from the individual memory cells, and a precharge circuit for precharging one bit line selected from among the plurality of bit lines in response to a precharge signal. It is determined whether charge in the precharged bit line is to be discharged based on a data content of a memory cell in the cell block selected by a row decoder connected to the bit line. The data content of the selected memory cell in the selected cell block is read out by a potential of the bit line. The memory device further includes at least one gate switching element connected in series to the memory cells of each of the cell blocks. The gate switching element, together with the memory cells of each cell block, forms a series circuit which has one end connected to an associated one of the bit lines and a second end connected to a low-voltage power supply. A mode setting circuit enables the gate switching element during precharging in a fast data reading mode, and disables the gate switching element during precharging in a slow data reading mode.
Inventors
- 👤 Hirokazu Kanma
- 👤 Akira Takenouchi
- 👤 Masahiro Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:22
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/12; G11C17/00; G11C17/08; G11C17/10; G11C17/12; G11C17/123
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
157 words
A data reading method for a semiconductor memory device for, after precharging a bit line in response to a precharge signal, determining whether a charge in said precharged bit line is to be discharged based on a data content of a memory cell connected to said precharged bit line and selected by a row decoder, thereby causing said data content of said selected memory cell to be read, said method comprising the steps of: in a fast data reading mode, enabling discharging of the charge in the bit line during precharging of the bit line based on said data content of said selected memory cell and reading data from said selected memory cell after precharging; and in a slow data reading mode, disabling discharging of the charge in the bit line during precharging of the bit line regardless of said data content of said selected memory cell and reading data from said selected memory cell after precharging.
Claim 2
Dependent Claim
157 words
A data reading method for a semiconductor memory device for, after precharging a bit line in response to a precharge signal, determining whether a charge in said precharged bit line is to be discharged based on a data content of a memory cell connected to said precharged bit line and selected by a row decoder, thereby causing said data content of said selected memory cell to be read, said method comprising the steps of: in a fast data reading mode, enabling discharging of the charge in the bit line during precharging of the bit line based on said data content of said selected memory cell and reading data from said selected memory cell after precharging; and in a slow data reading mode, disabling discharging of the charge in the bit line during precharging of the bit line regardless of said data content of said selected memory cell and reading data from said selected memory cell after precharging.
Claim 3
Dependent Claim
204 words
A semiconductor memory device comprising: a plurality of cell blocks each having at least one memory cell; a plurality of bit lines for reading data from the individual memory cells; a precharge circuit for precharging one bit line selected from among said plurality of bit lines in response to a precharge signal, wherein whether a charge in said precharged bit line is to be discharged is determined based on a data content of a memory cell in a cell block selected by a row decoder connected to the bit line, thereby causing said data content of said selected memory cell in said selected cell block to be read; at least one gate switching element connected in series to said at least one memory cell of each of said cell blocks, said gate switching element together with said at least one memory cell of each cell block forming a circuit having one end connected to an associated one of said bit lines and a second end connected to a low-voltage power supply; and a mode setting circuit for enabling said gate switching element during precharging in a fast data reading mode, and disabling said gate switching element during precharging in a slow data reading mode.
Claim 4
Dependent Claim
204 words
A semiconductor memory device comprising: a plurality of cell blocks each having at least one memory cell; a plurality of bit lines for reading data from the individual memory cells; a precharge circuit for precharging one bit line selected from among said plurality of bit lines in response to a precharge signal, wherein whether a charge in said precharged bit line is to be discharged is determined based on a data content of a memory cell in a cell block selected by a row decoder connected to the bit line, thereby causing said data content of said selected memory cell in said selected cell block to be read; at least one gate switching element connected in series to said at least one memory cell of each of said cell blocks, said gate switching element together with said at least one memory cell of each cell block forming a circuit having one end connected to an associated one of said bit lines and a second end connected to a low-voltage power supply; and a mode setting circuit for enabling said gate switching element during precharging in a fast data reading mode, and disabling said gate switching element during precharging in a slow data reading mode.
Claim 5
Dependent Claim
65 words
The semiconductor memory device according to claim 2, wherein said mode setting circuit receives an operation-mode setting signal and a discharge signal complementary to the precharge signal, and, based on said operation-mode setting signal and said discharge signal, enables said gate switching element during precharging in said fast data reading mode, and disables said gate switching element during precharging in said slow data reading mode.
Claim 6
Dependent Claim
49 words
The semiconductor memory device according to claim 3, wherein said gate switching element is a discharge transistor, and said at least one memory cell in each of said cell blocks comprises a plurality of series-connected memory transistors, said discharge transistor being connected in series to said series-connected memory transistors.
Claim 7
Dependent Claim
58 words
The semiconductor memory device according to claim 3, wherein said at least one memory cell in each of said cell blocks comprises a plurality of series-connected memory transistors, and said gate switching element is a select transistor for selecting an associated one of said cell blocks, said series-connected memory transistors being connected in series to said select transistor.
Claim 8
Dependent Claim
49 words
The semiconductor memory device according to claim 2, wherein said gate switching element is a discharge transistor, and said at least one memory cell in each of said cell blocks comprises a plurality of series-connected memory transistors, said discharge transistor being connected in series to said series-connected memory transistors.
Claim 9
Dependent Claim
58 words
The semiconductor memory device according to claim 2, wherein said at least one memory cell in each of said cell blocks comprises a plurality of series-connected memory transistors, and said gate switching element is a select transistor for selecting an associated one of said cell blocks, said series-connected memory transistors being connected in series to said select transistor.
Claim 10
Dependent Claim
120 words
A control circuit for a semiconductor memory device, the memory device operating in a fast mode for reading data according to a clock signal having a first period and in a slow mode for reading data according to the clock signal having a second, longer period, the control circuit comprising: a signal generator for generating the clock signal having the first period and the second period, and an operation mode setting signal for designating to the memory device reading data in the fast mode and the slow mode; and a processing unit for outputting a read enable signal for enabling a read operation of the memory device and a precharge signal for initiating a precharge operation of the memory device.
Claim 11
Dependent Claim
120 words
A control circuit for a semiconductor memory device, the memory device operating in a fast mode for reading data according to a clock signal having a first period and in a slow mode for reading data according to the clock signal having a second, longer period, the control circuit comprising: a signal generator for generating the clock signal having the first period and the second period, and an operation mode setting signal for designating to the memory device reading data in the fast mode and the slow mode; and a processing unit for outputting a read enable signal for enabling a read operation of the memory device and a precharge signal for initiating a precharge operation of the memory device.
Claim 12
Dependent Claim
77 words
The control circuit of claim 8, further comprising: a precharge circuit for precharging a selected one of a plurality of bit lines of the memory device in response to the precharge signal, wherein a charge in the selected bit line is discharged based on a data content of a memory cell of a selected cell block of the memory device connected to the bit line, such that the data content of the selected memory cell is read.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-21 | 2010-12-21 | 2011-06-22 | $7700.00 | Window Closed / Lapsed |