US5914504A
Expired / Lapsed
US
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DRAM applications using vertical MISFET devices
Assignee: Imec
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Filing: 1996-06-17
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Granted: 1999-06-22
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Expires: 2016-06-17
Abstract
Abstract The present invention relates to RAM circuits comprising memory cells and logic circuitry wherein each of the memory cells comprise at least one Vertical MISFET device comprising a stack of several layers a source layer, a channel layer, a drain layer and a capacitor on the top of the stack of several layers of the Vertical MISFET device.
Inventors
- 👤 Carlos Jorge Ramiro Proenca Augusto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 15:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/63; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6728; H10D30/674; H10D30/6741; H10D30/6743; H10D62/00; H10D62/80; H10D62/82; H10D62/822; H10D62/83; H10D64/00; H10D64/60; H10D64/62; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0195; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
86 words
A RAM circuit comprising memory cells and logic circuitry, each of said memory cells comprising at least one Vertical MISFET transistor comprising a stack of multiple layers comprising: a source layer having a first orientation; a drain layer also having said first orientation; a channel layer disposed between said source layer and said drain layer, said channel layer also having said first orientation, wherein a semiconductor heterojunction is formed between said source layer and said channel layer; and a capacitor on the top of said stack.
Claim 2
Dependent Claim
86 words
A RAM circuit comprising memory cells and logic circuitry, each of said memory cells comprising at least one Vertical MISFET transistor comprising a stack of multiple layers comprising: a source layer having a first orientation; a drain layer also having said first orientation; a channel layer disposed between said source layer and said drain layer, said channel layer also having said first orientation, wherein a semiconductor heterojunction is formed between said source layer and said channel layer; and a capacitor on the top of said stack.
Claim 3
Dependent Claim
32 words
The RAM circuit of claim 1, wherein said channel layer is undoped or lightly doped and said source layer has an undoped or lightly doped region near the source layer/channel layer interface.
Claim 4
Dependent Claim
17 words
The RAM circuit of claim 2 wherein the Vertical MISFET transistor is a Vertical Heterojunction MISFET transistor.
Claim 5
Dependent Claim
40 words
The RAM circuit of claim 2 further comprising a gate which at least partially overlaps said source, said channel, and said drain layers, said gate being separated by an insulating layer from said source, said channel, and said drain layers.
Claim 6
Dependent Claim
30 words
The RAM circuit of claim 4, wherein said gate has a second orientation, said second orientation being at an angle of about 90 degrees with respect to said first orientation.
Claim 7
Dependent Claim
23 words
The RAM circuit of claim 5, wherein the logic circuitry is selected from the group consisting of planar transistors and Vertical MISFET transistors.
Claim 8
Dependent Claim
19 words
The RAM circuit of claim 6, wherein the logic circuitry additionally comprises one or more Vertical Heterojunction MISFET transistors.
Claim 9
Dependent Claim
35 words
A RAM circuit comprising memory cells and logic circuitry, each of said memory cells comprising at least two of the Vertical MISFET transistors of claim 5 on top of each other with a capacitor therebetween.
Claim 10
Dependent Claim
44 words
The RAM circuit of claim 8, wherein the two Vertical MISFET transistors are complementary, wherein the bottom transistor is selected from the group consisting of PMOS and NMOS transistors and the top transistor is selected from the group consisting of NMOS and PMOS transistors.
Claim 11
Dependent Claim
23 words
The RAM circuit of claim 8, wherein the logic circuitry is selected from the group consisting of planar transistors and Vertical MISFET transistors.
Claim 12
Dependent Claim
18 words
The RAM circuit of claim 10, wherein said logic circuitry comprises one or more Vertical Heterojunction MISFET transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-21 | 2002-12-21 | 2003-06-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-21 | 2006-12-21 | 2007-06-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-21 | 2010-12-21 | 2011-06-22 | $7700.00 | Window Closed / Lapsed |