Multi-processor power saving system which dynamically detects the necessity of a power saving operation to control the parallel degree of a plurality of processors

Claim 2

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by having one CPU take over a process performed by another CPU depending on an occurrence of an event regarding power management of the computer system, said parallel degree switching means further including means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 3

A system according to claim 1, wherein said parallel degree switching means comprises means for detecting a heat value of said computer or a heat value of each of said CPUs, and means for dynamically changing the parallel degree in accordance with the heat value.

Claim 4

A system according to claim 1, wherein said power supply comprises means for detecting that said power supply is an AC power supply or a battery, and said parallel degree switching means comprises means for setting the parallel degree to be high when said power supply is an AC power supply, and setting the parallel degree to be low when said power supply is a battery.

Claim 5

A system according to claim 1, further comprising means for detecting a residual capacity of a battery, and wherein said parallel degree switching means comprises means for, when said power supply is a battery, changing the parallel degree in accordance with the residual capacity of the battery.

Claim 6

A system according to claim 1, wherein said parallel degree switching means comprises means for changing the parallel degree in accordance with a load state of a CPU in operation.

Claim 7

A system according to claim 1, wherein said parallel degree switching means comprises means for controlling supply of a clock signal or power to each of said CPUs, and means for stopping supply of a clock or power to a CPU at halt.

Claim 8

A system according to claim 1, wherein said plurality of CPUs comprise CPUs having the same power consumption and the same performances.

Claim 9

A system according to claim 1, wherein said plurality of CPUs comprise CPUs having different power consumptions or different performances.

Claim 10

The system according to claim 1, further comprising a process management table constituted by a process number, an execution process number, a program counter, a stack pointer, general registers, floating point operation registers, an integer operation flag save area, and a floating point operation flag save area, and the parallel degree switching means performs the take over from one CPU to another CPU by using the process table.

Claim 11

The system according to claim 1, wherein said parallel degree switching means includes CPU operation/stop data indicating operation/stop of each CPU, and monitors the current operation state of each CPU.

Claim 12

The system according to claim 1, wherein said parallel degree switching means further includes means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by performing a predetermined algorithm comprising the operations of: upon detection of the establishment of a CPU operation halt condition, the parallel degree switching means activates an interrupt signal to a CPU to be ceased (CPU A); CPU A issues an interrupt response bus cycle to acquire an interrupt vector; the parallel degree switching means returns data indicating a halt request, as an interrupt vector, to the CPU A; CPU A saves, in response to the data indicating a halt request, its internal state including a program counter, a stack pointer, various general registers, floating point operation register, and various operation flags, into a process management table; the parallel degree switching means selects a CPU for a take-over process (CPU B) from other CPUs in operation to let it take over the process performed by the CPU A, and interrupts the CPU B; the CPU B makes an interrupt response in response to the interrupt; the parallel degree switching means returns the interrupt vector indicating task take-over to the CPU B; and the CPU B updates the process management table, loads the internal state of the CPU A, and branches to an address of the program counter stored as the internal state of the CPU A.

Claim 13

The system according to claim 1, further comprising: a power supply for supplying power to said plurality of CPUs; and means for stopping a supplement of power from the power supply to a non-operated CPU.

Claim 14

The system according to claim 1 further comprising means for changing a speed of at least one of said plurality of CPUs in accordance with occurrence of the event regarding power management of the computer system.

Claim 15

A multiprocessor type computer system, comprising: a plurality of CPUs having different power consumptions and different throughputs; means for measuring a temperature of each of said CPUs; means for calculating a load on each of said CPUs; means for setting an operation environment; and CPU switching means for switching CPUs by having one CPU take over a process performed by another CPU depending on an occurrence of an event regarding power management of the computer system, the CPU switching means further including means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 16

A multiprocessor type computer system, comprising: a plurality of CPUs having different power consumptions and different throughputs; means for measuring a temperature of each of said CPUs; means for calculating a load on each of said CPUs; means for setting an operation environment; and CPU switching means for switching CPUs by having one CPU take over a process performed by another CPU depending on an occurrence of an event regarding power management of the computer system, the CPU switching means further including means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 17

A system according to claim 14, wherein said power supply comprises an AC power supply or a battery, and said switching means comprises means for operating a CPU having a high throughput when said power supply is an AC power supply, and for operating a CPU having a lower power consumption when said power supply is a battery.

Claim 18

A system according to claim 14, wherein said power supply comprises a battery, and means for detecting a residual capacity of the battery, and said CPU switching means comprises means for operating a CPU having a high throughput when the battery residual capacity detected by said detection means is smaller than a predetermined value, and for operating a CPU having a low power consumption when the battery residual capacity is not more than the predetermined value.

Claim 19

A system according to claim 14, wherein said CPU switching means comprises means for detecting a heat value of said computer or a heat value of each of said CPUs, and means for switching CPUs to be operated in accordance with the heat value.

Claim 20

A system according to claim 14, wherein said CPU switching means comprises means for controlling supply of a clock signal or power to each of said CPUs, and stops supply of a clock or power to a CPU at halt.

Claim 21

The system according to claim 14, further comprising a process management table constituted by a process number, an execution process number, a program counter, a stack pointer, general registers, floating point operation registers, an integer operation flag save area, and a floating point operation flag save area, and the CPU switching means performs the take over from one CPU to another CPU by using the process table.

Claim 22

The system according to claim 14, wherein said CPU switching means includes CPU operation/stop data indicating operation/stop of each CPU, and monitors the current operation state of each CPU.

Claim 23

The system according to claim 14, wherein said CPU switching means further includes means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by performing a predetermined algorithm comprising the operations of: upon detection of the establishment of a CPU operation halt condition, the CPU switching means activates an interrupt signal to a CPU to be ceased (CPU A); CPU A issues an interrupt response bus cycle to acquire an interrupt vector; the CPU switching means returns data indicating a halt request, as an interrupt vector, to the CPU A; CPU A saves, in response to the data indicating a halt request, its internal state includes a program counter, a stack pointer, various general registers, floating point operation register, and various operation flags, into a process management table; the CPU switching means selects a CPU for a take-over process (CPU B) from other CPUs in operation to let it take over the process performed by the CPU A, and interrupts the CPU B; the CPU B makes an interrupt response in response to the interrupt; the CPU switching means returns the interrupt vector indicating task take-over to the CPU B; and the CPU B updates the process management table, loads the internal state of the CPU B, and branches to an address of the program counter stored as the internal state of the CPU A.

Claim 24

The system according to claim 14, further comprising: a power supply for supplying power to each of the CPUs; and means for stopping a supplement of power from the power supply to a non-operated CPU.

Claim 25

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; a process management table constituted by a process number, an execution process number, a program counter, a stack pointer, general registers, floating point operation registers, an integer operation flag save area, and a floating point operation flag save area; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by having one CPU take over a process performed by another CPU by using the process management table memory and depending on an occurrence of an event regarding power management of the computer system, said parallel degree switching means further including means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 26

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; a process management table constituted by a process number, an execution process number, a program counter, a stack pointer, general registers, floating point operation registers, an integer operation flag save area, and a floating point operation flag save area; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by having one CPU take over a process performed by another CPU by using the process management table memory and depending on an occurrence of an event regarding power management of the computer system, said parallel degree switching means further including means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 27

The system according to claim 23, further comprising: a power supply for supplying power to each of the CPUs; and means for stopping a supplement of power from the power supply to a non-operated CPU.

Claim 28

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 29

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 30

The system according to claim 25, further comprising: a power supply for supplying power to each of the CPUs; and means for stopping of supplement of power from the power supply to a non-operated CPU.

Claim 31

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; a memory storing CPU operation/stop data indicating operation or stop state of each CPU; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by monitoring the current operation state of each CPU by referring to the memory, said parallel degree switching means further including means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 32

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; a memory storing CPU operation/stop data indicating operation or stop state of each CPU; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by monitoring the current operation state of each CPU by referring to the memory, said parallel degree switching means further including means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by a predetermined algorithm comprising the operations of: comparing the number of CPUs set by a user with the number of CPUs determined from a CPU temperature, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs set by the user is larger than that determined from the CPU temperature; and comparing the number of CPUs determined from a battery residual capacity with the number of CPUs determined from the CPU temperature if it is determined that the user has not set the number of CPUs to be operated, and giving priority to the number of CPUs determined from the CPU temperature if the number of CPUs determined from the battery residual capacity is larger than the number of CPUs determined from the CPU temperature.

Claim 33

The system according to claim 27, further comprising: a power supply for supplying power to each of the CPUs; and means for stopping a supplement of power from the power supply to a non-operated CPU.

Claim 34

The system according to claim 27, further comprising means for stopping supplement of a clock signal to at least one of said plurality of CPUs in accordance with an occurrence of an event regarding power management of the computer system.

Claim 35

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; a process management table constituted by a process number, an execution process number, a program counter, a stack pointer, general registers, floating point operation registers, an integer operation flag save area, and a floating point operation flag save area; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by performing a predetermined algorithm comprising the operations of: upon detection of the establishment of a CPU operation halt condition, the parallel degree switching means activates an interrupt signal to a CPU to be ceased (CPU A); CPU A issues an interrupt response bus cycle to acquire an interrupt vector; the parallel degree switching means returns data indicating a halt request, as an interrupt vector, to the CPU A; CPU A saves, in response to the data indicating a halt request, its internal state including a program counter, a stack pointer, various general registers, floating point operation register, and various operation flags, into a process management table; the parallel degree switching means selects a CPU for a take-over process (CPU B) from other CPUs in operation to let it take over the process performed by the CPU A, and interrupts the CPU B; the CPU B makes an interrupt response in response to the interrupt; the parallel degree switching means returns the interrupt vector indicating task take-over to the CPU B; and the CPU B updates the process management table, loads the internal state of the CPU A, and branches to an address of the program counter stored as the internal state of the CPU A.

Claim 36

A multiprocessor type computer system, comprising: a plurality of central processing units (CPUs) for parallel processing; a process management table constituted by a process number, an execution process number, a program counter, a stack pointer, general registers, floating point operation registers, an integer operation flag save area, and a floating point operation flag save area; and parallel degree switching means for changing the number of CPUs to be simultaneously operated by controlling operation/non-operation for each of said plurality of CPUs by performing a predetermined algorithm comprising the operations of: upon detection of the establishment of a CPU operation halt condition, the parallel degree switching means activates an interrupt signal to a CPU to be ceased (CPU A); CPU A issues an interrupt response bus cycle to acquire an interrupt vector; the parallel degree switching means returns data indicating a halt request, as an interrupt vector, to the CPU A; CPU A saves, in response to the data indicating a halt request, its internal state including a program counter, a stack pointer, various general registers, floating point operation register, and various operation flags, into a process management table; the parallel degree switching means selects a CPU for a take-over process (CPU B) from other CPUs in operation to let it take over the process performed by the CPU A, and interrupts the CPU B; the CPU B makes an interrupt response in response to the interrupt; the parallel degree switching means returns the interrupt vector indicating task take-over to the CPU B; and the CPU B updates the process management table, loads the internal state of the CPU A, and branches to an address of the program counter stored as the internal state of the CPU A.

Claim 37

The system according to claim 30, further comprising: a power supply for supplying power to each of the CPUs; and means for stopping a supplement of power from the power supply to a non-operated CPU.