US5912850A
Expired / Lapsed
US
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Multi-port RAM with shadow write test enhancement
Assignee: RPX Clearinghouse LLC
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Filing: 1997-07-24
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Granted: 1999-06-15
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Expires: 2017-07-24
Abstract
Abstract A multi-port RAM (random access memory) includes RAM cells which are coupled to respective row and column lines of each port. RAM cells selected by signals on the row and column lines of a port store binary data. A ground level voltage is applied onto selected column lines in a shadow write mode. Any short between the active column lines and the column lines in shadow write will result in a significant error voltage being applied to the active column line and invalid read will result. Shorts between column lines from different ports are sensitized.
Inventors
- 👤 Steven William Wood
- 👤 Garnet Frederick Randall Gibson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:55
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/025; G11C29/04; G11C29/50; G11C8/00; G11C8/16; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
100 words
A multi-port RAM (random access memory) comprising: an array of RAM cells of m rows by n columns, m and n being integers, the RAM cells being coupled to respective row and column lines of each port; means for selecting RAM cells for storing binary data by applying signals on row and column lines; means for selecting RAM cells for reading binary data by applying signals on respective row and column lines; and test means comprising voltage driver for driving a predetermined level voltage onto selected column lines to cease data read in selected column lines in a test mode.
Claim 2
Dependent Claim
100 words
A multi-port RAM (random access memory) comprising: an array of RAM cells of m rows by n columns, m and n being integers, the RAM cells being coupled to respective row and column lines of each port; means for selecting RAM cells for storing binary data by applying signals on row and column lines; means for selecting RAM cells for reading binary data by applying signals on respective row and column lines; and test means comprising voltage driver for driving a predetermined level voltage onto selected column lines to cease data read in selected column lines in a test mode.
Claim 3
Dependent Claim
36 words
The multi-port RAM of claim 1, wherein the voltage driver comprises a plurality of switching devices, each being coupled with the respective column line and a voltage terminal to which the predetermined level voltage is fed.
Claim 4
Dependent Claim
42 words
The multi-port RAM of claim 2, wherein the switching device comprises a FET (field effect transistor), the drain-source of which is coupled between the respective column line and the voltage terminal, a control signal is applied to the gate of the FET.
Claim 5
Dependent Claim
19 words
The multi-port RAM of claim 3, further comprising means for providing a ground level voltage to the voltage terminal.
Claim 6
Dependent Claim
18 words
The multi-port RAM of claim 1, wherein the RAM cell comprises storage means for storing differential binary data.
Claim 7
Dependent Claim
32 words
The multi-port RAM of claim 5, wherein the column lines comprises differential bit lines, the storage means of the RAM cells of each column are coupled to the respective differential bit lines.
Claim 8
Dependent Claim
13 words
The multi-port RAM of claim 1, further comprising means for selecting a port.
Claim 9
Independent Claim
106 words
A method for testing a multi-port RAM comprising an array of RAM cells of m rows by n columns, m and n being integers, the RAM cells being coupled to respective row and column lines of each port, the RAM cells storing binary data being selected by signals on the row and column lines, the binary data stored in the RAM cells selected by signals on the row and column lines being read, the method comprising the steps of: selecting column lines; and driving a predetermined level voltage onto the selected column lines to cease data read in the selected column lines in a test mode.
Claim 10
Independent Claim
106 words
A method for testing a multi-port RAM comprising an array of RAM cells of m rows by n columns, m and n being integers, the RAM cells being coupled to respective row and column lines of each port, the RAM cells storing binary data being selected by signals on the row and column lines, the binary data stored in the RAM cells selected by signals on the row and column lines being read, the method comprising the steps of: selecting column lines; and driving a predetermined level voltage onto the selected column lines to cease data read in the selected column lines in a test mode.
Claim 11
Dependent Claim
21 words
The method of claim 8, further comprising the step of running test patterns through non-selected column lines in the test mode.
Claim 12
Dependent Claim
28 words
The method of claim 8, wherein the step of driving comprises the step of driving a ground level voltage onto the selected column lines in the test mode.
Claim 13
Dependent Claim
57 words
The method of claim 8, further comprising the steps of: driving a ground level voltage onto the selected column lines in the test mode, the selected column lines being adjacent to a non-selected column line, data read in the selected column lines being ceased; and running test patterns through the non-selected column lines in the test mode.
References Cited (Backward Citations)
US5561638A
Cited
US5742557A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-06-14 | 2002-12-14 | 2003-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-06-14 | 2006-12-14 | 2007-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-06-14 | 2010-12-14 | 2011-06-15 | $7700.00 | Window Closed / Lapsed |