Demodulator phase correction for code division multiple access receiver

Claim 2

A Code Division Multiple Access, CDMA, receiver comprising means for receiving a coherent CDMA signal including k, where k<or=1, encoded data channels and at least one pilot channel, the k data channels being encoded using mutually orthogonal codes, and a demodulator for decoding a desired one of the k data channels and one of the at least one pilot channels, the demodulator including a switch for switching the desired data channel and the pilot channel to a plurality of accumulator circuits for demodulating the desired data channel the switch being controlled by an orthogonal code of the desired data channel during accumulation.

Claim 3

A Multi-Code, MC, Code Division Multiple Access, CDMA, receiver comprising means for receiving and despreading a coherent CDMA signal including k, where k>or=to 1, encoded data channels and at least one pilot channel, the k data channels being encoded using mutually orthogonal codes, and a demodulator for decoding a desired set of N data channels out of the k data channels and one of the at least one pilot channels, the demodulator including a switch for switching the desired set of N data channels and the pilot channel to a plurality of accumulator circuits for demodulating a desired data channel, the switch being controlled by an orthogonal code of the desired data of N data channels during accumulation.

Claim 4

A Multi-Code, MC, Code Division Multiple Access, CDMA, receiver comprising means for receiving and despreading a coherent CDMA signal including k, where k>or=to 1, encoded data channels and at least one pilot channel, the k data channels being encoded using mutually orthogonal codes, and a demodulator for decoding a desired set of N data channels out of the k data channels and one of the at least one pilot channels, the demodulator including a switch for switching the desired set of N data channels and the pilot channel to a plurality of accumulator circuits for demodulating a desired data channel, the switch being controlled by an orthogonal code of the desired data of N data channels during accumulation.

Claim 5

The receiving of claim 1 or 2, respectively, wherein the mutually orthogonal codes are Walsh codes.

Claim 6

The CDMA receiver of claim 1 wherein after the accumulator circuits squaring circuits are applied for performing the channel weighting.

Claim 7

The CDMA receiver of claim 4 wherein the squaring circuits are implemented using a look-up table.

Claim 8

The CDMA receiver of claim 4 wherein when the switch is left in a predetermined state, a non-coherent signal energy is determined.

Claim 9

The receiver of claim 1 or 2, respectively, wherein the k data channels include at least a Q and an I signal channel.

Claim 10

The receiver of claim 1 or 2, respectively, being part of a user station of a CDMA or MC-CDMA system, respectively, including at least one base station and a plurality of user stations.

Claim 11

The receiver of claim 1 or 2, respectively, being part of a base station of a CDMA or MC-CDMA system, respectively, including at least one base station and a plurality of user stations.

Claim 12

The MC-CDMA receiver of claim 2 wherein the switch includes a first switch for switching the desired set of N data channels and the at least one pilot channel to a Plurality of accumulator circuits for demodulating the desired set of N data channels, the first switch being controlled by an orthogonal code of the desired set of N data channels during accumulation, a second switch alternately switching intermediate accumulation results to the input of a fast transformation circuitry at N times the symbol rate R b of the data channels and wherein the fast transformation circuitry is optimized to the orthogonal code.