Patent US5901225A successfully refreshed from Google Patents.
US5901225A
Expired / Lapsed
US
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System and method for performing software patches in embedded systems
Assignee: Microsemi Semiconductor US Inc
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Filing: 1996-12-05
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Granted: 1999-05-04
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Expires: 2016-12-05
Abstract
Abstract A system and method for performing software patches for embedded system devices in which the firmware of the system is included in non-alterable storage of the device. The patch mechanism provides a means for finding firmware errors, prototyping fixes to the errors and/or prototyping new functionality of the firmware of the embedded system. The system comprises an embedded system device coupled to an external memory. The device includes a non-alterable memory, including firmware, coupled to a processor. The device further includes a relatively small amount of patch RAM within the device also coupled to the processor. The patches are loaded from the external memory into the patch RAM. The device further includes a means for determining if one or more patches are to be applied. If the device detects a patch to be applied, the system loads the patch from the external memory into the patch RAM. The device also includes a breakpoint register. When the value of the program counter of the processor equals the value in the breakpoint register, a patch insertion occurs, i.e., the processor deviates from executing firmware to executing patch instructions. Preferably, the embedded system device comprises a single integrated circuit. The processor may include a plurality of breakpoint registers. The patch may be encrypted for increased security. Multiple patches may be chained together, and run-time patch replacement is contemplated.
Inventors
- 👤 Mark A. Ireton
- 👤 Gerald Champagne
- 👤 Corbett A. Marler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 21:03
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/322; G06F9/328; G06F8/00; G06F8/60; G06F8/65; G06F8/66
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
134 words
A embedded system device configured to receive a software patch, comprising: a processor including a breakpoint register and a program counter, each adapted for storing a value; a non-alterable memory coupled to said processor, wherein said non-alterable memory includes instructions executable by said processor; and an alterable memory coupled to said processor configured to store a patch, wherein said patch comprises patch instructions executable by said processor; wherein said processor is configured to deviate from executing said instructions included in said non-alterable memory to execute said patch instructions stored in said alterable memory when said program counter value equals said breakpoint register value, wherein said patch is encrypted prior to being loaded into said alterable memory, and wherein said device is configured to decrypt said patch when loading said patch into said alterable memory.
Claim 2
Dependent Claim
134 words
A embedded system device configured to receive a software patch, comprising: a processor including a breakpoint register and a program counter, each adapted for storing a value; a non-alterable memory coupled to said processor, wherein said non-alterable memory includes instructions executable by said processor; and an alterable memory coupled to said processor configured to store a patch, wherein said patch comprises patch instructions executable by said processor; wherein said processor is configured to deviate from executing said instructions included in said non-alterable memory to execute said patch instructions stored in said alterable memory when said program counter value equals said breakpoint register value, wherein said patch is encrypted prior to being loaded into said alterable memory, and wherein said device is configured to decrypt said patch when loading said patch into said alterable memory.
Claim 3
Dependent Claim
15 words
The device as recited in claim 1, wherein said device comprises a single integrated circuit.
Claim 4
Dependent Claim
27 words
The device as recited in claim 1, wherein said device is configured to load said patch into said alterable memory from a memory external to said device.
Claim 5
Dependent Claim
61 words
The device as recited in claim 1, wherein said device further comprises: patch presence detection means for indicating a presence of a patch in an external memory; wherein said device is coupled to said patch presence detection means and is configured to load said patch into said alterable memory if said patch presence detection means indicates the presence of said patch.
Claim 6
Dependent Claim
22 words
The device as recited in claim 1, wherein said patch further comprises a patch offset indicating the location of said patch instructions.
Claim 7
Dependent Claim
21 words
The device as recited in claim 1, wherein said patch further comprises a patch size indicating the size of said patch.
Claim 8
Dependent Claim
59 words
The device as recited in claim 1, wherein said patch further comprises a breakpoint address for loading into said breakpoint register, wherein said processor deviates from executing said instructions included in said non-alterable memory to execute said patch instructions stored in said alterable memory when said program counter value equals said breakpoint register value loaded into said breakpoint register.
Claim 9
Dependent Claim
20 words
The device as recited in claim 1, wherein said patch further comprises variables used in operation of said patch instructions.
Claim 10
Dependent Claim
38 words
The device as recited in claim 1, wherein said patch further comprises startup instructions, wherein said processor is configured to execute a plurality of said startup instructions after loading said patch and prior to executing said patch instructions.
Claim 11
Dependent Claim
57 words
The device as recited in claim 1, wherein said non-alterable memory includes breakpoint handler instructions, wherein said processor is configured to deviate from executing said instructions included in said non-alterable memory to execute said breakpoint handler instructions when said program counter value equals said breakpoint register value, wherein said breakpoint handler instructions branch to said patch instructions.
Claim 12
Dependent Claim
95 words
The device as recited in claim 1, wherein said device comprises a plurality of breakpoint registers each containing a value, wherein said alterable memory is configured to store a plurality of patches each comprising patch instructions, wherein said plurality of patches correspond to said plurality of breakpoint registers, wherein said processor is configured to deviate from executing said instructions included in said non-alterable memory to execute said patch instructions of one of said plurality of patches stored in said alterable memory when said program counter value equals a corresponding one of said breakpoint register values.
Claim 13
Dependent Claim
27 words
The device as recited in claim 1, wherein said device further comprises: means for receiving a direct memory access transfer of said patch into said alterable memory.
Claim 14
Dependent Claim
35 words
The device as recited in claim 1, wherein said processor comprises an interrupt signal generated when said program counter value equals said breakpoint register value, wherein said deviation occurs in response to said interrupt signal.
Claim 15
Dependent Claim
29 words
The device as recited in claim 1, wherein said device further comprises: command interface logic operably coupled to said processor to control loading said patch into said alterable memory.
Claim 16
Dependent Claim
23 words
The device as recited in claim 14, wherein said breakpoint register value is loaded into said breakpoint register using said command interface logic.
Claim 17
Dependent Claim
134 words
A embedded system configured to receive a software patch, comprising: an embedded system device comprising: a processor including a breakpoint register and a program counter, each containing a value; a non-alterable memory coupled to said processor, wherein said nonalterable memory includes instructions executable by said processor; and an alterable memory coupled to said processor configured to store a patch, wherein said patch comprises patch instructions executable by said processor; and an external memory operably coupled to said device including said patch; wherein said processor is configured to load said patch from said external memory to said alterable memory and to execute said patch, wherein said patch is encrypted prior to being loaded into said alterable memory, and wherein said device is configured to decrypt said patch when loading said patch into said alterable memory.
Claim 18
Dependent Claim
134 words
A embedded system configured to receive a software patch, comprising: an embedded system device comprising: a processor including a breakpoint register and a program counter, each containing a value; a non-alterable memory coupled to said processor, wherein said nonalterable memory includes instructions executable by said processor; and an alterable memory coupled to said processor configured to store a patch, wherein said patch comprises patch instructions executable by said processor; and an external memory operably coupled to said device including said patch; wherein said processor is configured to load said patch from said external memory to said alterable memory and to execute said patch, wherein said patch is encrypted prior to being loaded into said alterable memory, and wherein said device is configured to decrypt said patch when loading said patch into said alterable memory.
Claim 19
Dependent Claim
22 words
The system as recited in claim 16, wherein said patch further comprises a patch offset indicating the location of said patch instructions.
Claim 20
Dependent Claim
21 words
The system as recited in claim 16, wherein said patch further comprises a patch size indicating the size of said patch.
Claim 21
Dependent Claim
59 words
The system as recited in claim 16, wherein said patch further comprises a breakpoint address for loading into said breakpoint register, wherein said processor deviates from executing said instructions included in said non-alterable memory to execute said patch instructions stored in said alterable memory when said program counter value equals said breakpoint register value loaded into said breakpoint register.
Claim 22
Dependent Claim
20 words
The system as recited in claim 16, wherein said patch further comprises variables used in operation of said patch instructions.
Claim 23
Dependent Claim
38 words
The system as recited in claim 16, wherein said patch further comprises startup instructions, wherein said processor is configured to execute a plurality of said startup instructions after loading said patch and prior to executing said patch instructions.
Claim 24
Independent Claim
230 words
A method for executing a patch in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes instructions executable by said processor, and an alterable memory coupled to said processor configured to store a patch, wherein a portion of said patch comprises patch instructions executable by said processor, the method comprising: initializing said program counter to a value; loading said breakpoint register with a breakpoint address; determining a presence of said patch after said initializing said program counter value and before said loading said breakpoint register; loading said patch into said alterable memory before said loading said breakpoint register if said patch is present; encrypting said patch prior to said initializing said program counter to a value; decrypting said encrypted patch during said loading said patch; fetching an instruction from said non-alterable memory at an address equal to said program counter value; incrementing said program counter in response to said fetching; executing said instruction; performing said fetching, said incrementing and said executing until said program counter value equals said breakpoint register value; deviating from said fetching, said incrementing and said executing when said program counter value equals said breakpoint address; executing a plurality of patch instructions of a patch included in said alterable memory in response to said deviating.
Claim 25
Independent Claim
230 words
A method for executing a patch in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes instructions executable by said processor, and an alterable memory coupled to said processor configured to store a patch, wherein a portion of said patch comprises patch instructions executable by said processor, the method comprising: initializing said program counter to a value; loading said breakpoint register with a breakpoint address; determining a presence of said patch after said initializing said program counter value and before said loading said breakpoint register; loading said patch into said alterable memory before said loading said breakpoint register if said patch is present; encrypting said patch prior to said initializing said program counter to a value; decrypting said encrypted patch during said loading said patch; fetching an instruction from said non-alterable memory at an address equal to said program counter value; incrementing said program counter in response to said fetching; executing said instruction; performing said fetching, said incrementing and said executing until said program counter value equals said breakpoint register value; deviating from said fetching, said incrementing and said executing when said program counter value equals said breakpoint address; executing a plurality of patch instructions of a patch included in said alterable memory in response to said deviating.
Claim 26
Independent Claim
28 words
The method as recited in claims 22, wherein said loading said patch comprises copying said patch from an external memory coupled to said device into said alterable memory.
Claim 27
Dependent Claim
16 words
The device as recited in claim 23, wherein said copying comprises said processor performing said copying.
Claim 28
Dependent Claim
16 words
The device as recited in claim 23, wherein said copying comprises a direct memory access transfer.
Claim 29
Dependent Claim
29 words
The method as recited in claim 22, wherein said patch comprises startup instructions, wherein the method further comprises executing said startup instructions prior to said loading said breakpoint register.
Claim 30
Dependent Claim
36 words
The method as recited in claim 22, wherein said patch comprises said breakpoint address, wherein said loading said breakpoint register with said breakpoint address comprises loading said breakpoint address from said patch into said breakpoint register.
Claim 31
Dependent Claim
37 words
The method as recited in claim 22, wherein said non-alterable memory further includes breakpoint handler instructions, the method further comprising: executing said breakpoint handler instructions after said deviating; said breakpoint handler instructions branching to said patch instructions.
Claim 32
Dependent Claim
22 words
The method as recited in claim 22, wherein said deviating comprises loading said program counter with the address of said patch instructions.
Claim 33
Dependent Claim
37 words
The method as recited in claim 22, wherein said deviating comprises forcing a branch instruction to said patch instructions when performing said fetching an instruction from said non-alterable memory when said fetching address is a predetermined address.
Claim 34
Dependent Claim
15 words
The method as recited in claim 22, wherein a single integrated circuit comprises said device.
Claim 35
Independent Claim
227 words
A method for executing a series of patches in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising: executing said firmware instructions; loading a first of said series of patches into said alterable memory; loading said breakpoint register with a first breakpoint address after said loading said first of said series of patches; deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address; executing said first of said series of patches in response to said deviating from said executing said firmware instructions; loading a second of said series of patches into said alterable memory; loading said breakpoint register with a second breakpoint address after said loading said second of said series of patches; deviating from said executing said first of said series of patches when said program counter value equals said second breakpoint address; executing said second of said series of patches in response to said deviating from said executing said first of said series of patches.
Claim 36
Independent Claim
227 words
A method for executing a series of patches in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising: executing said firmware instructions; loading a first of said series of patches into said alterable memory; loading said breakpoint register with a first breakpoint address after said loading said first of said series of patches; deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address; executing said first of said series of patches in response to said deviating from said executing said firmware instructions; loading a second of said series of patches into said alterable memory; loading said breakpoint register with a second breakpoint address after said loading said second of said series of patches; deviating from said executing said first of said series of patches when said program counter value equals said second breakpoint address; executing said second of said series of patches in response to said deviating from said executing said first of said series of patches.
Claim 37
Independent Claim
229 words
A method for executing a series of patches in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising: loading a first of said series of patches into said alterable memory; loading a second of said series of patches into said alterable memory; loading said breakpoint register with a first breakpoint address after said loading said first and second of said series of patches; executing said firmware instructions; deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address; executing said first of said series of patches in response to said deviating from said executing said firmware instructions; loading said breakpoint register with a second breakpoint address after said loading said second of said series of patches; deviating from said executing said first of said series of patches when said program counter value equals said second breakpoint address; executing said second of said series of patches in response to said deviating from said executing said first of said series of patches.
Claim 38
Independent Claim
229 words
A method for executing a series of patches in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising: loading a first of said series of patches into said alterable memory; loading a second of said series of patches into said alterable memory; loading said breakpoint register with a first breakpoint address after said loading said first and second of said series of patches; executing said firmware instructions; deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address; executing said first of said series of patches in response to said deviating from said executing said firmware instructions; loading said breakpoint register with a second breakpoint address after said loading said second of said series of patches; deviating from said executing said first of said series of patches when said program counter value equals said second breakpoint address; executing said second of said series of patches in response to said deviating from said executing said first of said series of patches.
Claim 39
Independent Claim
193 words
A method for replacing a patch in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising: loading a first patch into said alterable memory; loading said breakpoint register with a first breakpoint address after said loading said first patch; executing said firmware instructions; deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address; executing said first patch in response to said deviating from said executing said firmware instructions; loading a second patch into said alterable memory; loading said breakpoint register with a second breakpoint address after said loading said second patch; deviating from said executing said first patch when said program counter value equals said second breakpoint address; executing said second patch in response to said deviating from said executing said first patch.
Claim 40
Independent Claim
193 words
A method for replacing a patch in an embedded system device comprising a processor including a breakpoint register and a program counter, each containing a value, a non-alterable memory coupled to said processor, wherein said non-alterable memory includes firmware instructions executable by said processor, and an alterable memory coupled to said processor configured to store said series of patches, wherein a portion of each of said series of patches comprises patch instructions executable by said processor, the method comprising: loading a first patch into said alterable memory; loading said breakpoint register with a first breakpoint address after said loading said first patch; executing said firmware instructions; deviating from said executing said firmware instruction when said program counter value equals said first breakpoint address; executing said first patch in response to said deviating from said executing said firmware instructions; loading a second patch into said alterable memory; loading said breakpoint register with a second breakpoint address after said loading said second patch; deviating from said executing said first patch when said program counter value equals said second breakpoint address; executing said second patch in response to said deviating from said executing said first patch.
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| 7.5 Years (Year 8) | 2006-05-03 | 2006-11-02 | 2007-05-04 | $3760.00 | Window Closed / Lapsed |
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