Semiconductor memory device capable of disconnecting an internal booster power supply from a selected word line in response to a test signal and testing method therefor

Abstract

Abstract There is provided disconnecting circuit for disconnecting an internal boosted power supply from a word line. At the time of testing, one of a plurality of word lines is selected therefrom and data on the "Low" level is written in a plurality of memory cells connected to the selected word line. Thereafter, the disconnecting circuit is activated such that the selected word line has high impedance. When there is a leakage current flowing from the word line due to a defect, the potential on the word line lowers rapidly after the word line is disconnected from the internal boosted power supply. Consequently, the data cannot be written properly in the memory cells any more. After a specified period of time has elapsed, data on the "High" level is written sequentially in the memory cells connected to the selected word line. Then, the same word line is selected again such that the data written in the memory cells connected to the word line is read therefrom. If the read data is on the "Low" level and erroneous, it follows that the data on the "High" level has not been written successfully. Therefore, it is judged that there is a leakage current flowing from the word line. In this manner, both testing time and testing cost can be reduced. Since a minimal leakage current that has conventionally been difficult to detect can be detected, testing ensures the removal of a potential defect becoming more evident as the semiconductor memory deteriorates with time.

Inventors

• 👤 Toshihiro Inokuchi
• 👤 Makoto Kojima

Bibliographic Details